TRD Electronics

1
TRD Status Meeting December 19, 2005

• TRAP
• OASE
• ORI
• GTU
• DCS

Volker Lindenstruth Chair of Computer Science
Kirchhoff Institute for PhysicsUniversity
Heidelberg, Germany Phone [phone]
9800 Fax [phone] Email ti_at_kip.uni-heide
lberg.de WWW www.ti.uni-hd.de
2
Trap Chip Preproduction Bad Yield Investigations
Wafertests with the TRAP chip showed quite
different yield depending on from which
production batch the chip came from. The two
patched wafer types showed quite high yield in
the range of 80. The so called preproduction
wafers contrarily had a very bad yield below
30. We observed one major issue Certain errors
occured cumulatively in the same areas on the
preproduction wafers. These areas were not
distributed uniformly over the entire wafer but
occured on certain positions. Especially the
overcurrent errors (errorcode 3) occured
cumulatively in the rows below the OASE chip and
decreased in the lower rows. We tried to
investigate in depth what the reason could be for
this bad yield of the so called preproduction
wafers. Therefore we looked for hot spots on the
chips.
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
3
Trap Chip Preproduction Bad Yield Investigations
Our first try with an infrared camera failed. We
then used a liquid crystal lacquer on the dies
which showed a very high heat gradient
sensitivity. With this lacquer we could see very
clearly hotspots on the chips under the
microscope with polarized light. We measured
four dies which have had overcurrent in the wafer
tests. One from wafer 4, which was a pilot run
wafer and three randomly chosen dies with
overcurrent from wafer 10, which was a
preproduction wafer. On the three preproduction
dies the hotspots lay always in the filter region
in a very limited area while on the wafer 4 chip
the hotspot lay in the cpu region. The following
imaged demonstrate that. The hot part of the chip
is black.
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
4
Trap Chip Preproduction Bad Yield Investigations
This picture shows a schematic view of the TRAP
chip
5
Trap Chip Preproduction Bad Yield Investigations
This is a photo from chip 3 on wafer 4 (pilot
run). It shows a hotspot in the middle of the
chip in the cpu region.
X
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
6
Trap Chip Preproduction Bad Yield Investigations
This is a photo from chip 9 on wafer 10. It shows
a hotspot in the filter region. This photo is a
screenshot from monitor. So quality is quite bad.
X
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
7
Trap Chip Preproduction Bad Yield Investigations
This is a photo from chip 11 on wafer 10. It
shows a hotspot in the filter region, too.
X
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
8
Trap Chip Preproduction Bad Yield Investigations
This is a photo from chip 14 on wafer 10. It
shows a hotspot in the filter region. too.
X
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
9
Trap Chip Preproduction Bad Yield Investigations
The photos from the lacquered dies show quite
well the positions of hot spots on the
dies. Allthough we could only test four dies
until now the accumulation of hotspots in the
filter region of the wafer 10 dies seems to
indicate a systematic phenomenon. The filter
region only contains standard cells but has a
very high std. cell density
Chair of Computer Science and Engineering /
Prof. Dr. Volker Lindenstruth /
http//www.kip.uni-heidelberg.de/ti/
10
Discussion with IMEC and UMC

• Detailed investigations at UMC really no
  signifficant difference between wafer runs
• We aggree that it is preprocessing not
  metallzation (inconsistent with bonding issues _at_
  FZK)
• UMC thinks it may be caused by OASEs TWELL
• Launch corner run ASAP and run a few versions
  without TWELL processing step

11
OASE Tests

• Two OASE reworked successfully
• Stable operation into Xilinx V2P MGT
• OASE requires M2M6 patch
• Test with TRAP Clock t.b.d.

12
Optical Link Test Setup
ACEX PCI
2.5Gb/s
TRAP
NI
Read compare the received data with the expected
Pseudorandom data with start words programmed by
the PC software, 1 event 300 packets of about 1
kB
850 nm
Opt. Cable
I2C/JTAG
PC
SCSN, Pretrigger
More than 100 Gbytes of data sent day night, no
errors. The next version of the optical board
expected tomorrow. Components ordered for 100
boards.
13
Optical Link
14
GTU

• Layout complete MSC failed to produce (after
  approving early version of Gerber data)
• Respin of entire PCB required ongoing,
  resulting in delay of 4 weeks
• Try to tape-out before 1.1.06 so that first PCBs
  (5day turn around) are _at_ KIP in KW2

15
DCS

• 100 units delivered, 5 (out of 5) tested OK
• 100 units delayed (KW2/06?)
• Ethernet Cabling t.b.d.
• Ethernet D-Link switch issue
• Has been used for months
• New version of same device does not work with DCS
  card
• First switch to show such behavior will be
  diagnosed (known since 2 days)