T0 Electronics Production Readiness Review

1
T0 Electronics Production Readiness Review

• W.H.Trzaskaon behalf of T0 team

HIP, Department of PhysicsUniversity of
Jyväskylä, Finland
2
Outline

• Introduction
• Shoebox amplifier, CFD (Jyväskylä)
• VDL (MEPhI)
• OR (MEPhI)
• Mean Timer (MEPhI)
• TVDC (KI ?)
• MPD (KI ?)
• FAN-OUT (KI ?)
• QTC (INR Tatiana Karavicheva)
• T0TU (INR Tatiana Karavicheva)
• NIMLVDS (INR Tatiana Karavicheva)
• Cabling, HV, LV, DCS (Tomasz Malkiewicz)

3
T0-C
4
T0-A
5
T0 electronics layout
6
Full chain readout testNovember 2005

• T0 time and amplitude digitized and stored with
  the latest version of TOF hardware (HPTDC)
• HV and laser attenuator under DCS
• CFD DCS prototype tested
• Next round of full chain tests scheduled
• Jan 06 Moscow
• Feb 06 Jyväskylä
• Mar 06 CERN

7
Time resolution of a single PMT channel
Results from November 2005 full-chain readout
test at CERN
At high multiplicities the final T0 resolution
will be considerably better than that of a single
PMT
T0/V0 Shoebox works very well!
8
Shoebox for T0 and V0

• T0 and V0 must provide TRD wake-up
• Wake-up must be generated inside L3
• Need for a box with electronics
• Jyväskylä part to split amplify pulses 3 mV
  3 V 0.6 600 pC (V.Lyapin)
• Heidelberg part to duplicate trigger logic for
  TRD (K. Oyama)

9
T0/V0 amplifier Internal Clamping
V.Lyapin 11.01.06
G 1
Va
Vb

-
Input

G 10
-
20 Ohm

-
G 10
10
Clamping has no significant effect on the
performance of the amplifier
11
Radiation test at Jyväskylä inAugust 2005
12
LDO Voltage Regulator UCC284DP-5 (Texas
Instrument) Broken at 100 krad exposure
13
TRDP FEB T0-A/C, V0-A/C-0..3
2 x 12 (T0) 2 x 32 (V0) 88 88 22 spares
120 total
14
Main features

• Based on ultra-wideband current-feedback
  operational amplifier OPA695
• max output current 100 mA, 4300V/usec slew rate
• gt450MHz bandwidth at higher gains (G 8) .
• Size 55 x 55 x 15 mm
• Power supply 6 V 0.1A and 6V 0.1 A
• Max power consumption 1.2 W
• Input SMA connector, 50 Ohm impedance
• Output 1 SMA connector gain 1 (direct output)
• Output 2 SMA connector, gain 10
• Output 3 2 pins, differential level analog
  signal with gain 10 to TRD discriminator

15
Shoebox amplifier cost estimate
Component name units per Ampl. subTotal
120   number of units to be made  
OPA695 1.10 2 264
UCC284 2.80 1 336
THS4503I 4.00 1 480
TPS7350 1.00 1 120
Resistors 0.04 26 125
Capacitors 0.20 14 336
Electrolytic capac. 4.10 8 3 936
Trimmers 2.10 3 756
BFR520 0.31 1 37
RClamp0502B 0.28 1 34
SMA connectors 8.20 3 2 952
Soldering 15.00 1 1 800
PCB production 35.00 1 4 200
    Total 15 376
16
Component costs (ampl.)
Component name units per Ampl. subTotal
120
OPA695 1.10 3 396
UCC284 2.80 1 336
TPS7350 1.00 1 120
Resistors 0.04 26 125
Capacitors 0.20 14 336
Electrolytic capac. 4.10 8 3,936
Trimmers 2.10 3 756
SMA connectors 8.20 3 2,952
Soldering 15.00 1 1,800
PCB production 35.00 1 4,200

Total 14,957
17
T0 fast electronics
18
Canberra CFD 6 or 12 needed _at_ 3 k per unit
19
Necessary modifications to CFD (to control
Threshold Walk via DCS)

• Installing SMC sockets
• Changing 2 resistors per channel
• Changing settings by external voltages instead of
  a build-in potentiometer
• Tested and works well

20
Canberra CFD 454 modification
Before
After
-5V
-5V
Threshold SMC connector
Threshold Check point
10 kOhm
1 kOhm
10 kOhm
1 kOhm
10 kOhm
10 kOhm
10 kOhm
To Threshold comparator
To Threshold comparator
100 Ohm
1 kOhm
100 Ohm
1 kOhm


21
Canberra 454 CFD
Features Four CF discriminators in a
single-width NIM 200 MHz count rate
capability 10001 dynamic range Typical walk
lt30 ps for 1001 dynamic range Selectable
fraction or leading edge operation Output
indicator LED 6 units needed if only one output
per PMT is used 12 units if also the
non-amplified will be used 3 000 per unit
(price in Finland with 0 VAT)
How to purchase electronics?
22
Variable Delay Line (VDL)
Parameters

• Number of independent delay channels in the
  single unit 4.
• Standard of input and output signals NIM.
• Signal plug SMC.
• Step of delay tuning 10 ps.
• Range of delay tuning 10 ns.
• Control code 10 bits.

The programmable delay unit is intended mainly
for equalizing the signal delays at the
individual channels of PMT before their delivery
to the ORA and ORC circuits. Moreover, the VDL
can be used for the choice of initial delay of TM
and TVDC units, and it can be used in all other
cases for precise remote tuning of delay.
23
VDL prototype (24 units needed)
24
Test results of VDL unit
25
Second VDL prototype in VME standard (24 channels
needed)
26
Main features

• Based on MC100EP195
• 4 independent channels
• VME standard 6U (233 x 160)
• Power supply 5V, 12V
• Dissipated power 8 W
• 4 inputs (1 per 1 channel),NIM standard, LEMO
  connectors
• 4 outputs per channel, NIM standard, LEMO
  connectors

27
Component costs( 8 units 6 main 2spare)

• item cost USD units
  per mod. subtotal
• Integrated circuits
  32 2000
• Resistors 0.04
  65 21
• Capacitors 0.2
  32 50
• LEMO connectors (single) 4.6 4
  148
• LEMO connectors (double) 19 8
  1216
• Soldering 66
  1 528
• PCB production 160 40 1
  400
• Mech.unit L.V.connector 50 1
  400
• Spare ICs 200
  32 200
• 
  TOTAL 4963 USD

28
Logical Unit OR (two needed)
Parameters

• Input signals are in NIM standard with the 10 ns
  duration
• Output signals are in NIM standards
• Jitter of the output signal is not more then 25
  ps
• The unit is controlled by the 12-bit code.

The logic unit is intended for generation of
common signal TOA (or TOC) using the signal from
12 CFD units (constant fraction discriminators).
Moreover, the logic unit provides the possibility
for precise tuning of delays in each PMT-CFD
channel by remote commutation of channels. The
time gating can be also provided with the use of
CLK signal.
29
OR prototype in CAMAC
30
Measured characteristics of the module OR
31
Logic module OR

• 12 inputs for timing signals from 12 CFDs delay
• Generates timing and logic signals synchronized
  to the first input signal within a 10 ps
  precision.
• Any input channel can be switched off by
  corresponding command coming via VME bus (in case
  of problems).
• STATUS of the module
• First prototype tested, non-satisfactory results
  large pick-ups
• New 4-layer PCB ready for production
• Completion of production of the second prototype
  expected in May 2006

32
Main features of the module OR

• Based on ICs MC100EL31
• Dimensions VME 6U (233 x 160)
• Power supply - 5V,12V,-5V,-2V
• Dissipated power 20 W
• 13 inputs in NIM standard (LEMO connectors)
• 5 outputs in NIM standard (LEMO connectors)

33
Component costs (2 modules 1 spare)
item cost USD units per
mod. subtotal Integrated circuits
44 1545
Transistors 1
36 108 Resistors
0.04 258
33 Capacitors 0.2
135 81 DIN64 connector
1.5 1 4.5
LEMO
connectors (single) 4.6 18
250 Soldering
60 1 180 PCB
production 1000 1
1500 Mech.unit LV connectors 50
1 150 Spare parts
30
200
TOTAL 4051.5

34
Mean Timer
Principle of operation
Center of gravity on the time axis of two signals
T0A and T0C in case of a fixed distance between
two arrays of detectors (T0A T0C )/2 is
independent of the position of the vertex
35
Mean Timer

• Input signals are in NIM standards of 10 ns
  duration
• Output signals are in NIM standard
• Jitter of the output signal is not more then 20
  ps
• The accuracy of timing (time binding to the
  middle point of time interval ranging within 3
  ns) is lt 20 ps.

36
Mean timer 1st prototype

• Generates precisioninteraction time thatdoes
  not depend onvertex position
• On-line check of T0 performance

37
Test results of Mean Timer prototype (CERN, June
2003)
38
Test results of the second prototype(with
generator, December 2004)
Some small changes in the printed board layout of
the Mean Timer are made for the final design.
39
Main features

• Based on ICs MC10EL
• Dimensions NIM standard
• Two units in one module (one spare)
• Power supply 5V, -5V,12V
• Dissipated power 1.2 W
• 2 inputs in NIM standard, LEMO connectors
• 2 outputs in NIM standard, LEMO connectors

40
Component costs (2 units 1 main 1 spare)

• item cost in USD
  units per mod. subtotal
• Integrated circuits
  6 120
• Resistors 0.04
  44 4
• Capacitors 0.2
  21 8
• LEMO connectors 4.6 8
  74
• Soldering 15
  1 30
• PCB production 100 1
  100
• Mechanics 100
  1 100
• Spare ICs 6
  60
• 
  TOTAL 496 USD

41
FAN-OUT
42
FAN-OUT main features

• 4 channels per module
• 3 outputs in each channel
• Max. output amplitude 5V (R50O)
• Rise time 1.8 ns
• Zero-level stability 0.5 mV
• Power consumption
• 5V 0,24 A
• -5V - 0,12 A
• -12V 0,2 A.
• MPD module has VME 1U width and 6U height.

43
FAN-OUT single unit cost estimate
44
Time stability of zero level (output 1 channel 1)
45
Out 1-1 Out 2-1 crosstalk after correction
46
TVDC electronic module, generating the trigger
signal of the events T0-vertex
47
TVDC diagram
C comparator UV univibrator DS discharge
switch ?? coincidence circuit ??
anticoincidence circuit CS charge switch BA
buffer amplifier BR buffer register OR
mixer.
48
TVDC main features

• range of conversion time intervals ?2,5 ns(5
  ns)
• quantization step 20 ps (for 8-bit conversion)
  
• dead time of conversion not more than 25 ns.
• VME interface based on FPGA Xilinx XC95108

Spectrum, characterizing the resolution of TVDC
module
The given parameters obtained with the use of
time-amplitude converter and flash ADC with the
digital discriminator for TO-vertex signal
generation.
49
TVDC cost estimation
50
Input signals to TVDC
51
Output signals of TVDC
52
Multiplicity Discriminator
53
MPD diagram
54
MPD main features

• Number of inputs 24
• Maximum amplitude of the signal at each input 3
  V, minimal duration 3 ns.
• The output signals at the (Semi-Central and
  Central outputs are in the NIM standard with the
  10 ns duration.
• The maximum amplitude of the signals at the Out1
  and Out2 are 3 V.
• Power supply
• 5V 0.24A
• -5V 1.09A
• 12V 0.05A
• -12V 0.05A
• MPD module has VME 1U width and 6U height. As
  the VME decoder is used a FPGA chip (XILINX
  XC95108).

55
MPD single unit cost estimate
56
Alternative solution for QTC slewing correction
in reverse
V.Lyapin 21.03.05
The time difference between LED and CFD is
proportional to the logarithm of amplitude. Our
test has confirmed that with TDC range of 50 ns
we get 5 accuracy of amplitude determination.
In the test Canberra 454 CFD and LeCroy 4416 B
LED were used. Further improved is possible (if
needed) by using Timing Filter Amplifier to
increase rise time of the analyzed pulses.
57
T0 Milestones
Milestone planned expected

636 Electronics PRR Dec-05 10-Feb-06
637 T0C detector test Jan-06 Feb-06
638 T0C ready for installation Apr-06 Apr-06
639 T0A ready for installation Jul-06 Jul-06