ALICE TRD Trigger

1
CBM Summary of FEE Meting
Volker Lindenstruth Kirchhoff Institute for
PhysicsChair of Computer Science University
Heidelberg, Germany Phone [phone]
9800 Fax [phone] Email ti_at_kip.uni-heide
lberg.de WWW www.ti.uni-hd.de
2
Agenda

• 0900 FOPI electronics specs and performance
  M. Ciobanu (GSI)
• 0915 FEE for HADES RPC's D. Belvers
  (Santiago)
• 0930 RPC FEE Specs for CBM A. Schüttauf (GSI)
• 0945 DLL based ASIC-TDC H. Deppe (GSI)
• 1000 TAC based ASIC-TDC H. Flemming (GSI)
• 1015 PLL prototyping in 2004 P. Fischer
  (Mannheim)
• 1030 A Campus-wide Time Synchronization System -
  BuTiS P. Moritz (GSI)
• 1045 Coffee break
• 1055 Gas detectors and electronics requirements
  H. Wessels (Münster)
• 1105 RICH electronics requirements S.
  Sadovsky (IHEP)
• 1110 FEE for a Straw based TRD V. Golovtsov
  (PNPI)
• 1125 Si-Strip FEE development status E. Atkin
  (Moscow)
• 1140 MEPHi facilities for radiation hardness
  tests A. Simakov (Moskow)
• 1145 Multi-purpose FEE Architecture V.
  Lindenstruth (KIP)
• 1200 Pre-amplifier / Shaper concepts R.
  Tielert (Kaiserslautern)
• 1215 Low power ADC concepts D. Muthers
  (Kaiserslautern)
• 1230 Low jitter clock recovery and high speed
  serial transmission
• S. Tontisirin (Kaiserslautern)
• 1245 FEE Communication / High Speed CAM U.
  Brüning (Mannheim)

3
Common Front-End Electronics
preFilter
digital Filter
Hit Finder
Backend Driver
PreAmp
ADC

• Si Strip
• Pad
• GEM's
• PMT
• APD's

Anti-AliasingFilter
Sample rate 10-100 MHz Dyn. range 8...gt12 bit
'Shaping' 1/t Tailcancellation Baselinerestorer
Hit parameter estimators Amplitude Time
Clustering Buffering Link protocol
Detector specific
generic
4
Technology Choice
A. Marchioro (CERN)
5
Over All Architecture
to/from next neighbor hit detection

• Hit Detector
• Leading Edge
• peak

N Pre- Amplifier Blocks
Programmable Finite State Machine
DATA-out
send
Fast Readout
DAC
start
Digital Pipeline
Hit TDC
TIMER
stop
Ain
CLOCK
we
Event Buffers
1..N
sample
WE
RE
Digital Filters
ADC

• different combinations
• sampling rate
• resoluion
• power

ANALOG FIFO
Analog Filter
to/from next neighbor hit detection
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Over All Architecture
Brüning
Trontisirin Brüning
Muthers
Tielert
Need global, synchronous time reference
Brüning
7
RPC-FEE1 and FEE2
FEE1
FEE2
8
FEE STEP3 board One-channel DB logic
R
MAX9601-2ch 500ps Propagation Delay
S4ch.
2k2
Trigger Out.
Amplifiers
In
BFT92 Wideband PNP Transistor
C
Latch enable
4 ch. out
BGA2712 MMIC Wideband (21dB 1GHz)
GALI-S66 Monolithic (18dB 2GHz)
TOF-Threshold
PECL- LVDS
C
MAX9601-2ch
PTN3311
C
TOT-Threshold
OPA690 Wideband Operat. Amplifier
TOT Integrator
SAMTEC 16 diff. pins

• Amplifier stage (analog stage)
• PHILIPS BGA2712 GALI-S66 (same as FOPI).
• Q/TOT stage with TI OPA690.
• Digital stage
• Dual MAXIM9601 comparator. Latch enable input
  used for cut and shape the output pulse .
• PECL-LVDS PHILIPS PTN3311 converter.
• PHILIPS BFT92 transistor for multiplicity trigger
  sum.

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An Array of DLLs
Running an array of M DLLs each with N elements
and also DLL controlled -- phase shifts between
these DLLs Bin size determined by TBin TRef
/ N TRef / M N number of DE M counts of DLLs 1
register with width N M E.g. An array of 4
DLLs deliver a Bin size of 25ps
PWR-Consumption increase to 6mW/Chan.
10
The TAC Core

• Digital delay chain
• Distributed RC-Network
• Voltage on Cout increases linear with time

11
Open Questions

• Open questions concerning both, TAC and DLL
  solution
• TDC resolution required?
• Single / double hit resolution?
• Double hit only flagged?
• Integration Level (Geometry)?
• Event rate to cope with (100 kHz)?
• Discriminator specs (time over threshold)?
• min. and max. signal length
• double hit resolution
• Temperature?
• Radiationhardness?
• Interfaces?
• Discriminators, clock distribution, DAQ

12
New chip TC3 with lager devices, PMOS pair,

• All MOS wider, but still minimum length for
  speed! This is bad for matching
• Detail of VCO (Ringoscillator)

current sources under wide power busses
VCO inverter
small inverter
interconnect between VCO stages(in light blue)
loads under wide power busses
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Summary

• Differential logic with diode-clamp load works
  (also at high speed). (This may not be the best
  solution!)
• Timer with ring oscillator, buffers, latches,
  works
• PLL locks
• Matching is a big issue.
• Observed mismatch cannot be reproduced by Monte
  Carlo Simulations.
• Consequences Submit matching test structures, or
  try out sizing
• Time bin width of 150 ps achieved at 100µA in
  0.35µm
• This leads to a single channel resolution (after
  correction of bin width) of s 55ps, including
  mismatch
• Expected improvement by going to 0.18µm is at
  least a factor of 2 (at same current, large
  devices)
• Another factor of two by increasing current.
• Can probably use a bit shorter MOS than in
  simulation..
• In total, s 15ps seams possible in 0.18µm with
  no further tricks.

14
GSI
A broadband propagation delay stabilization scheme
Optical Receiver (Detector)
Echoed stream propagation delay
3-Port Circulator
Pilot Delay Control
Variable Optical Delay
Laser Diode/Modulator
Optical Receiver (Detector)
MPX Stream with Pilot Signal
Forward stream propagation delay
The optical delay is by nature broadband,
covering a whole waveband (1310 or 1550nm)
15
GSI
Conclusion

• Use of broadband optical rf-links and single
  mode fibers are
• mandatory, most components can be purchased
  from stock
• The fiber properties need careful attention to
  reach 100ps_at_1km
• A BuTiS- like system will surely be needed for
  FAIR accelerators
• BuTiS has campus-wide capabilities for
  realtime
• synchronisation and timing
• At present conceptual design stage, system
  modifications can be
• realized without costly modifications
• It can be build with moderate costs at the
  beginning, and later
• extended to a very sophisticated topology

This presentation was brief but we re
open Your ideas and participation are welcome
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CROS3 Structure
Detector
Detector
FEE-1
Pre-Amp
Pre-Amp
FEE-16
Pre-Amp
Pre-Amp
FEE- 1
FEE-16
Digitizer
Digitizer
Digitizer
Digitizer
Serializer
Serializer
Serializer
Serializer
Copper Link 200Mb/sec
Copper Link
200Mb/sec
Concentrator 1
Concentrator N
Optical Link 1 Gb/ sec
Custom Electronics On Detector
L1 System Buffer 1
L1 System Buffer N
Custom Electronics In Counting Room
PCI Bus 130 MByte/ sec
L2 System Processor
Standard Electronics
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Conclusion
CROS3 Readout System can be proposed as
initial prototype of the TRD FEE The physical
packaging of the FEE is dependent on the
detector construction The digitizing granularity
should be increased if possible
It is more
preferably to have no cable run between the
Amplifier-Shaper-Discriminator and Digitizer to
decrease the system overall cost The analog part
has two possibilities for TRD Straw ASIC
1. Existed
ASD-BLR or ASDQ or ?
2. New ASIC such as 0.25 µm CMOS with the
cost of 60K per Design Run The digital part
of FEE is proposed to be based on Xilinx FPGA
LVDS signaling interconnect technology for short
distance data path Optical link technology for
long distance data path

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• Nearest plans I (2005/06)

• Development of building blocks for data-driven
  architecture, according to UMC CMOS 0.18 µm.
  Prototyping via Europractice (MPW).These blocks
  are
• Preamp
• Amplitude (slow) antialiasing and dynamic range
  saving shaper
• Timing (fast), hit defining shaper
• Low offset high-speed comparator both for hit
  finder and ADC. Studying both clocked and
  non-clocked options
• Threshold DAC (6-8 bit)
• Fast low-bit (46 or 8 bit ?) ADC
• Analog Derandomizer (deadtime free analog unit
  with n-inputs and m-outputs, ngtm)
• Rail-to-rail op amp (high speed buffer)
• Common issues are low power consumption,
  reasonable speed chip area

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• Nearest plans II (2005/06)

• Design and production (via MPW) of a test purpose
  chip for SST prototyping, according to AMIS CMOS
  0.35 µm rules Issues are face-to-face interface
  to Si strip prototype, cost effective design
• Lab tests of ICs manufactured
• Radiation hardness tests of ICs
• Development of FPGA based digital processing
  prototype

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TOTAL FASILITIES for FEE Rad Hard Tests

• Reasonable total ? radiation doze 10Mrad (E
  1MeV)
• Max. neutrons flux 3x109 n/cm2s
• (E 1,5MeV)
• Max. electrons flux 1011e/cm2s
• (E 10MeV)
• Ions particle energy 300 keV
• (B, O, N .)

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Conclusions

• PreAmp for 12 bit resolution 72 dB SNR and THD
• gt 72 dB loop gain 34 dB closed loop gain
  106 dB _at_ fT 40 MHz
• 1 LSB 245 µV gt 310 e _at_ Cfb 200fF
• Thermal noise of feedback resistor//capacitor _at_
  Cfb 200fF 150 µV (kT/C)
• Input referred noise of PreAmp is amplified by
  A 1 Cfb/ Cshunt 100 ( 40dB)
• gt 150 µV / 100 1.5 µV !!! (including pick up)
• Differential input helps to reduce pick up of
  noise irradiation
• Separate PreAmp chip should be attached very
  close to detector pad in order to reduce Cshunt
• Pulse shaping by zero of PreAmp transfer
  function reduces required dynamic range and
  hence saves power
• High order lowpass (Gm/C) filter is natural
  companion of AD-converter/digital chip

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Common ADC (Muthers)
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Common ADC (Muthers)
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Low Jitter Clock Recovery (Tontisirin)
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Clock and Timing distribution

• Fiber optics have become a commodity
• High speed readout serial anyway
• Use of glas as media simplifies grounding
• Half- and full diplex almost same price
• DCS functionality requires negligible fraction of
  downlink
• Use available uplink and fraction of downlink for
  DCS network (and others)
• Multi gigabit deserializers require very stable,
  low jitter clock recovery
• Why not use serial infrastructure also for clock
  and time distribution
• ? advanced optical serializer/deserializer

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OASE
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Ternary CAM Cell

• Save 20 of area by optimized design
• store 1/0 for a 1
• store 0/1 for a 0
• store 0/0 for dont care (cell does not
  participate in match calculation)
• Cell size is 10.82 µm x 2.69 µm

write
match
power down
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Status Plans

• Layouts of crucial (dense) blocks is done CAM
  cells, Flipflops, row decoder (F. Giesens
  Diploma Thesis)
• Most simulations (typical parameters) are
  done.Speed is gt500MHz for a CAM with 512 rows
  (parasitics of busses included)
• We plan to submit an 512 x 18 bit block (testing
  maximum speed needs full size!).Layout area of
  this core will be 0.3mm x 1.4mm
• Testing will be done by setting all input bits
  reading all output bits with shift
  registers.Timing will be generated by several
  external fast strobe signals.This stuff will be
  synthesized (with help from Rechnerarchitektur)
• We are confident to be ready until April 24.

done
missing
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Submission Plans

• Boundary condition 5x5 mm2

ADC Test structures (Muthers) PLL structures
(Tontisirin)
Full Custom CAM Test Structures DAC Ring
Oscillator Peter Fischer

• Boundary condition 1.5x1.5 mm2

FC CAM Fischer
TsT PeFi
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Summary

• First CBM FEE Meeting
• Technology Baseline Choice UMC 180nm
• Many existing building blocks and developments
• Several key issues/items identified
• Preamplifier
• ADC
• Clock Recovery (good enough for ToF?)
• Serializer
• Integration with BuTis
• Two MPW submissions foreseeable
• April 5x5 mm2 some space left
• June MiniASIC 1.5x1.5 mm2
• We need a FEE recess soon to discuss many of the
  outstanding preamplifier issues

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Thank You
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