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Status of HV power supply the Brick

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a flipflop that delays data signal by one internal clock cicle (50nsec) ; in the ... If no other problems show up, the brick currently in Pisa is considered to be ... – PowerPoint PPT presentation

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Title: Status of HV power supply the Brick


1
Status of HV power supply- the Brick -
  • Marco Incagli - INFN Pisa

2
Update since last TEM at CERN
  • The HV power supply will be built in Italy
  • Problems in HV controller as of CERN meeting of
    feb 7/8 2005
  • the HV controller has a potential problem in the
    VHDL code
  • This problem, observed in the code by a CAEN
    engineer, by Franco Spinella and by Vladimir
    Koutsenko, shows up in the simulation, but it was
    not verified experimentally
  • More tests were asked in order to check if the
    problem is real or not

3
Tests in thermal chamber
  • The brick was put in a thermal chamber and cycled
    from -40o to 60o no anomalous behaviour observed

4
The potential problem depends upon the relative
timing between the internal HV clock, the LeCroy
(slow control) clock and the LeCroy data
HV clock (20MHz) LeCroy clock (100-500
kHz) LeCroy data
100 msec
50 nsec
Expanded view
5
Forcing the error
  • Simulation says that the brick should not work if
    the slow control clock arrives later than the
    data
  • To force the error, we had to artificially delay
    the LeCroy clock signal with respect to the
    LeCroy data signal by adding 25 meters (!) of
    twisted cable on the clock wires.

6
  • In this extreme configuration, the brick does not
    work, as expected from simulation!

Return word (RX) is missing
CLOCK
DATA
96 nsec
7
Safety margins
  • What prevents LeCroy clock from coming after
    LeCroy data (condition for the error to appear)?
  • The data signal from JINF arrives to HV 6-8 nsec
    after the LeCroy clock . Always true?
  • The internal path in the LeCroy FPGA delays data
    wrt clock by 272psec . Dangerous!
  • CAEN inserted (without notifying us!) a flipflop
    that delays data signal by one internal clock
    cicle (50nsec) in the new version we have asked
    to add another flipflop to increase the safety
    margin .

8
Conclusions - I
  • The HV controller VHDL code, although not
    formally perfect, works correctly in the current
    configuration thanks to the extra FlipFlop
  • The controller is now in CAEN to be modified
    adding a second safety FF and including some
    improvements in the slow control commands
    suggested by me and by A.L.
  • Next week the controller will be back in Pisa for
    new tests. A test period at CERN in march will be
    planned.
  • Our collegues from Annecy and Madrid (RICH) have
    asked to have the brick for additional tests.

9
Conclusions - II
  • If no other problems show up, the brick currently
    in Pisa is considered to be the QM and will be
    tested for Space Qualification in Italy (Terni)
    or in Spain (Madrid) as soon as the mechanics is
    ready
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