Multicycle Datapath

1

• Multi-cycle Datapath

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Single Cycle Review
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Instruction Flow

• What are some of the main steps in the
  instruction execution? (refer to previous slide)
• Is this an efficient use of hardware? Why or why
  not?
• Do we really need 2 adders?

4
Multicycle Implementation

• Key elements (How many cycles is this? What are
  they?)

5
Examples

• add 1,2,3
• lw 2,10(3)
• sw 2,10(3)
• beq 7,8,40
• j 0x2ABCDEF

We will be ignoring the control signals for now!
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add 1,2,3
1.
2.
3.
4.
IR MemPC PC PC 4
A 1st Reg Src B 2nd Reg Src
ALUout A B
Rdest ALUOut
4 clock cycles for an ADD
7
lw 2,10(3)
1.
2.
3.
4.
5.
IR MemPC PC PC 4
A Addr Reg Src
ALUout A Imm.
MDR MemALUOut
Rdest MDR
5 clock cycles for a Load Word
8
sw 2,10(3)
1.
2.
3.
4.
IR MemPC PC PC 4
A Addr Reg Src B Store Reg Src
ALUout A Imm.
MemALUOut B
4 clock cycles for a Load Word
9
beq 7,8,40
1.
2.
3.
4.
IR MemPC PC PC 4
A 1st Reg Src B 2nd Reg Src
if (AB) ? PC ALUOut
3 clock cycles for a Branch Equal
10
j 0x2ABCDEF
1.
2.
3.
4.
IR MemPC PC PC 4
Decode Jump 1
PC PC31-28 (IR25-0ltlt2
3 clock cycles for a Jump
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CPI Revisited

• Now you see why we have such a thing as effective
  CPI.
• Different instruction types have different time
  requirements.
• And we havent even talked about floating-point
  instructions yet!

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Multicycle in MIPS (basic, w/o JUMP)
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Instruction Steps

• Instruction fetch (IF)
• Instruction decode and register fetch (ID/RF)
• Execution, EA Comp., or Branch Completion (EX)
• Memory access or R-type completion (MEM/WB)
• Memory read completion (WB)

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1. IF

• Hardware
• Instruction Memory
• PC Adder
• Instruction Register

• Operation
• IR MemoryPC
• PC PC 4

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Complete Multicycle Datapath (IF)
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2. ID/RF

• Operation
• A RegIR25-21
• B RegIR20-16
• ALUOut PC (sign-extend (IR15-0 ltlt 2

• Hardware
• Instruction Register
• Register File
• Registers A B
• Sign Extension
• Shift by 2
• ALU ALUOut

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Complete Multicycle Datapath (ID/RF)
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3. EX

• Operation
• Memory reference
• ALUOut A sign-extend (IR15-0)
• Arithmetic/Logic
• ALUOut A op B
• Branch
• if (AB) then PC ALUOut
• Jump
• PC PC31-28 (IR25-0ltlt2)

• Hardware
• ALU
• ALUOut
• PC
• PC Shift

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Complete Multicycle Datapath (EX)
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4. MEM ( also R-type WB)

• Operation
• Memory reference
• MDR MemoryALUOut
• or
• MemoryALUOut B
• Arithmetic/Logical
• RegIR15-11 ALUOut

• Hardware
• MDR
• Data memory
• B
• Register File
• ALUOut

R-type WB
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Complete Multicycle Datapath (MEM)
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5. WB (memory type)

• Operation
• Load
• RegIR20-16 MDR

• Hardware
• Register file
• MDR

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Complete Multicycle Datapath (WB)
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A Word About Pipelining

• Note the overlap of stages in different types of
  instructions
• Can we exploit this?

IF ID/RF EX MEM WB
25
MC Datapath with Control
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Complete MC Datapath
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Defining the Control

• MC is more complex cuz instruction is executed
  in a series of steps
• MC datapath must specify both control signals and
  next step in sequence.
• 2 different techniques for specifying control
• finite state machine
• microprogramming
• Both allow detailed implementation to be
  synthesized by a CAD system

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Defining the State Machine

• Consists of a set of states and directions on how
  to change states
• Each state also specifies a set of output that
  are asserted when the machine is in that state.
• Each state takes 1 cc
• Initial two states will be common for all
  instructions (why?)
• Steps 3-5 will differ, depending on instruction
  class
• FSM will return to initial state to begin next
  fetch

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Finite State Machine Control
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FSM Diagram for IF ID/RF
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Multicycle Datapath
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Control Block Diagram
Combinational Control logic
outputs inputs
Data path control outputs
Next state
State register
Inputs from instruction register opcode field
40
New MC Datapath with Exception Handling
41
New States for Exception Handling
IntCause 1 CauseWrite ALUSrcA 0 ALUSrcB
01 ALUOp 01 EPCWrite PCWrite PCSource 11
11
IntCause 0 CauseWrite ALUSrcA 0 ALUSrcB
01 ALUOp 01 EPCWrite PCWrite PC Source 11
10
To state 0 to begin next instruction
42
Complete FSM with Exception Handling