The Processor: Datapath

1
22342 - Computer Organization Assembly Language
Chapter 4
The ProcessorDatapath Control
2
Stored Program Architecture

• Instruction Cycle
• Fetch an instruction from memory
• Decode the instruction
• Get the operands
• Execute the instruction
• Where is the next instruction?
• Program Counter (PC)
• Instruction Pointer (IP)
• Where is the operand?

3
CPU

• Datapath
• Control Unit

Register File
CU
4
General-Purpose Register Organization
R1
R2
R3
R4
R5
R6
R7
MUX
MUX
A
B
ALU
5
General-Purpose Register Organization
OPR Operation
00000 Transfer A
00001 Increment A
00010 Add A B
00101 Subtract A - B
00110 Decrement A
01000 AND A and B
01010 OR A and B
01100 XOR A and B
01110 Complement A
10000 Shift right A
11000 Shift left A
Examples
Operation OPR ASEL BSEL DSEL
R1 ? R2 - R3
R4 ? SHL R4
6
General-Purpose Register Organization
OPR Operation
00000 Transfer A
00001 Increment A
00010 Add A B
00101 Subtract A - B
00110 Decrement A
01000 AND A and B
01010 OR A and B
01100 XOR A and B
01110 Complement A
10000 Shift right A
11000 Shift left A
Trivial view of Opcode Operands
Examples
Operation OPR ASEL BSEL DSEL
R1 ? R2 - R3 00101 010 011 001
R4 ? SHL R4 11000 100 000 100
7
Memory Interface

• Address / Data Buses
• Read / Write Control
• Bidirectional /UnidirectionalData Bus

22
ByteByteByteByte
26
ByteByteByteByte
Addr
Read
Data
Write
Data
Data
8
Building a Datapath
Write a program compile it. Where do you want
to put it? Where is the first instruction? What
comes out of memory? Where to perform
operation? Where are the operands? Who well tell
us which reg? Where to store result? Can we save
this reg to mem?

• Datapath Elements

Opcode Operands
9
Building a Datapath

• Datapath Elements

At what address?
10
Building a Datapath
How can we read it back?
11
Building a Datapath
Finished executing instruction. Where is the
next instruction? Why 4?
4
MUX
12
Building a Datapath
How can we add immediate? What if it is 8-bit
negative?
4
Opcode Operand immediate
MUX
Sign Extend
13
Building a Datapath
What about JMP Rel Disp? It can be positive
or negative!
4
Opcode Relative Displacement
MUX
MUX
Sign Extend
14
Building a Datapath
4
Shift Left 2
PC
Addr
Data Memory
MUX
MUX
Addr
Data
Data
Instruction Memory
Data
Sign Extend
15
Building a Datapath
MUX
Why the shift?
4
Shift Left 2
PC
Addr
Data Memory
MUX
MUX
Addr
Data
Data
Instruction Memory
Data
Sign Extend
16
Building a Datapath
MUX
4
Shift Left 2
Why not use ALU instead of another adder?
PC
Addr
Data Memory
MUX
MUX
Addr
Data
Data
Instruction Memory
Data
Sign Extend
17
Adding Control Signals to the Datapath
0 MUX 1
4
Shift Left 2
PC
Addr
Data Memory
1 MUX 0
0 MUX 1
Addr
Data
Data
Instruction Memory
Opcodeetc
Data
Sign Extend
Control Unit
Cy, Z, etc
18
Adding Control Signals to the Datapath
0 MUX 1
4
Shift Left 2
PC
Addr
Data Memory
1 MUX 0
0 MUX 1
Addr
Data
Data
Instruction Memory
Data
Sign Extend
Control Unit
19
A Simple Implementation Scheme

• ALU Control

ALU Control Lines Operation
0 0 0 0 AND
0 0 0 1 OR
0 0 1 0 Add
0 1 1 0 Subtract
0 1 1 1 Set on Less Than
1 1 0 0 NOR
slt R1, R2, R3
Cy 1 ? Carry from last adder Z 1 ?
The result 0
20
A Simple Implementation Scheme

• Instruction Format
• Arithmetic/Logic

Rd Rs Funct Rt
Funct ALU Operation ALU Cntrl Lines
100000 Add 0010
100010 Subtract 0110
100100 AND 0000
100101 OR 0001
101010 SLT 0111
Example
21
A Simple Implementation Scheme

• Instruction Format
• Load Immediate

Rt Value
16 bits (can be positive or negative)
Example R1 12
22
A Simple Implementation Scheme

• Instruction Format
• Load Memory

Rt M Rs Addr
32 bits
16 bits (can be positive or negative)
Example R6 M R4 1
23
A Simple Implementation Scheme

• Instruction Format
• Store Memory

M Rs Addr Rt
Example M R7 2 R9
24
A Simple Implementation Scheme

• Instruction Format
• JE Operation

If Rs Rt then PC PC 4Addr
PC is already incremented
Example
25
Final Datapath Design
0 MUX 1
4
Shift Left 2
Rs
PC
Rt
Addr
Data Memory
1 MUX 0
0 MUX 1
Addr
Data
Data
Rt
MUX
Rd
Instruction Memory
Data
Offset, Addr, Immediate
Sign Extend
26
Program Setup

• Write a Program
• Assemble it
• Store it in Memory

Example
0 4 8
3 4 0 1 0 0 0 A
0 0 2 1 0 8 2 0
1 0 2 1 F F F F
27
Datapath Operation
CLK PC I-Mem

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

0
TM
Adder MUX
PC Adder
TAdder
Reg ASel
Reg CSel
Reg CLD
ALU MUX
ALU Ctrl
Mem MUX
Data A
TReg
Sign Ext
ALU
TALU
Data C
TReg
28
Datapath Operation
CLK PC I-Mem

• How Fast Can the Clock Be?

0
TM
Adder MUX
Tclk
PC Adder
Reg ASel
Reg CSel
Reg CLD
ALU MUX
ALU Ctrl
Mem MUX
Data A
TReg
Sign Ext
ALU
TALU
Data C
TReg
29
Datapath Operation
CLK PC I-Mem

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

4
0
Adder MUX
PC Adder
4
Reg ASel
0
Reg CSel
1
Reg CLD
ALU MUX
ALU Ctrl
2
Mem MUX
Data A
0
Data B
ALU
10
Data C
10
30
Datapath Operation
CLK PC I-Mem

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

8
4
PC Adder
8
PC Adder 2
Adder MUX
Reg ASel
1
Reg CSel
1
Reg CLD
ALU MUX
ALU Ctrl
2
Data A
10
Data B
10
ALU
20
31
Datapath Operation
CLK PC I-Mem

• How Fast Can the Clock Be?

8
4
TM
PC Adder
8
PC Adder 2
Adder MUX
Reg ASel
1
Reg CSel
1
Reg CLD
ALU MUX
ALU Ctrl
2
Data A
10
TReg
Data B
10
ALU
20
TALU
32
Datapath Operation
CLK PC I-Mem

• How Fast Can the Clock Be?

8
4
TM
PC Adder
8
Tclk
TAdder
PC Adder 2
TAdder
Adder MUX
Reg ASel
1
Reg CSel
1
Reg CLD
ALU MUX
ALU Ctrl
2
Data A
10
TReg
Data B
10
ALU
20
TALU
33
Single-Cycle Implementation
CLK PC I-Mem

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

i
Reg ASel
Reg CSel
Reg CLD
ALU MUX
ALU Ctrl
Mem MUX
Data A
Sign Ext
ALU
D-Mem
Data C
34
Single-Cycle Implementation
CLK PC I-Mem

• Clock Speed?

i
TM
Reg ASel
Tclk
Reg CSel
Reg CLD
ALU MUX
ALU Ctrl
Mem MUX
Data A
TReg
Sign Ext
ALU
TALU
D-Mem
TM
Data C
TReg
35
Single-Cycle Implementation

• Example
• TM 200 picoseconds
• TALU 100 picoseconds
• TAdder 100 picoseconds
• TReg 50 picoseconds
• Fastest Clock?

Load Immediate/ALU Tclk gt TM 2 TReg
TALU
Load Memory Tclk gt 2 TM 2 TReg TALU
Store Memory Tclk gt 2 TM TReg TALU
Type Delay
LI / ALU 400 ps
LD 600 ps
ST 550 ps
Cond. Jump 350 ps
Conditional Jump Tclk gt Max
TM TReg TALU
2 TAdder
Tclk ps ? GHz
36
Multicycle Implementation

• Instructions take different number of clock
  cycles
• Functional units can be shared within the
  execution of a single instruction

37
Multicycle Implementation

• Some registers are not visible to the programmer

IR
X
PC
Result
Y
4
MDR
Sign Extend
Shift Left 2
Exercise Can you do all the previous instruction
here?
38
Multicycle Implementation

• Some registers are not visible to the programmer

IR
X
Memory
Result
PC
Y
4
MDR
Sign Extend
Shift Left 2
39
Multicycle Datapath Operation
1
CLK PC

• Fetch Instruction

0
MemRd
Tclk
IRLD
IR
Mem Out
TM
X MUX
Y MUX
0
ALU Ctrl
2 (Add)
ALU
TALU
PC MUX
PCLD
40
Multicycle Datapath Operation
2
CLK PC

• Fetch Instruction
• Decode Instruction
• Get Operands

4
0
MemRd
IRLD
IR
3401000A (LDI R1, 10)
Mem Out
Tclk
Reg ASel
XLD
X
Data A
TReg
Sign Ext
41
Multicycle Datapath Operation
3
CLK PC

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

4
IR
3401000A (LDI R1, 10)
XLD
X
0
X MUX
Y MUX
2
ALU Ctrl
2 (Add)
Tclk
ResultLD
Result
ALU
TALU
42
Multicycle Datapath Operation
4
CLK PC

• Fetch Instruction
• Decode Instruction
• Get Operands
• Execute it

4
IR
3401000A (LDI R1, 10)
ResultLD
Result
10
Reg CSel
1
C MUX
Reg CLD
Tclk
TReg
Tclk
43
Multicycle Implementation

• Example
• TM 200 picoseconds
• TALU 100 picoseconds
• TAdder 100 picoseconds
• TReg 50 picoseconds
• Fastest Clock?

Load Immediate/ALU 4 Clocks
Load Memory 5 Clocks
Store Memory 4 Clocks
Type Instr. Mix
LI / ALU 52
LD 25
ST 10
Cond. Jump 13
Conditional Jump 3 Clocks
Tclk ps ? GHz
44
Control Implementation
Datapath Control Signals ALU Operation, MUX
Selection,Memory Rd/Wr, etc
Control Unit CU
Data Processing Unit DPU or Datapath


Datapath Status Signals IR Fields, ALU Flags
45
Control Implementation

• Hardwired
• Standard Logic Components
• Fast
• Not Flexible, i.e. Difficult to Change Control
  Operation
• Microprogrammed
• Memory-Based
• Speed Function of Memory (slower than hardwired)
• Flexible Design

46
Control Implementation

• Hardwired
• FiniteStateMachine

Control Unit
CombinationalControlLogic
Datapath Control Outputs



State Register
Datapath Control inputs

47
Microprogrammed Control Implementation

• Each Linein the Micro-ProgramExecutesMicro-Op
  erations(in 1 Clock)
• Fetch,Decode,ExecuteCycle

Control Unit
Microprogram Counter
Microprogram Memory (Microstore)
ALU Operation, MUX Selection,Memory Rd/Wr, etc
48
Microprogram Control Unit

• Datapath Control Signals

C19 PC MUX Selects ALU or Result
C18 PC Load PC loads a new value
C17 Mem MUX Selects Result or PC
C16 Mem RD Memory read operation
C15 Mem WR Memory write operation
C14 IR LD IR loads a new value
C13 MDR LD MDR loads a new value
C12 RegC MUX Selects Rt or Rd fields
C11 DataC MUX Selects MDR or Result
C10 Reg WR Register write operation
C9 X LD X loads a new value
C8 Y LD Y Loads a new value
C7 X MUX Selects PC or X
C6 Y MUX1 Selects 4, Y, Sign Ext or Shift Left 2
C5 Y MUX0 Selects 4, Y, Sign Ext or Shift Left 2
C4 ALU3 Selects ALU operation
C3 ALU2 Selects ALU operation
C2 ALU1 Selects ALU operation
C1 ALU0 Selects ALU operation
C0 R LD Result loads a new value
49
Microprogram Control Unit
Opcode
MAP
IR
Funct
MUX
ConditionSelect
ZCyetc
µPC
1
µProgram Memory
C19
C0
50
Microprogram Control Unit

• Fetch Instruction

IR ? MPC PC ? PC 4
µPC M0 S1 S0
C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4
C3 C2 C1 C0
0
1



51
Microprogram Control Unit

• Decode / Get Operands

IR ? MPC PC ? PC 4
X ? RegIR2521 Y ? RegIR2016
µPC M0 S1 S0
C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4
C3 C2 C1 C0
0 1 1 1 0 1 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0 1
0
1

8

8
Opcode 0 Funct 100010
52
Microprogram Control Unit

• Execute Instruction

IR ? MPC PC ? PC 4
X ? RegIR2521 Y ? RegIR2016
R ? X Y
µPC M0 S1 S0
C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4
C3 C2 C1 C0
0 1 1 1 0 1 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0 1
0
1

8
9
1 1
1 0 0
8
Opcode 0 Funct 100010
53
Microprogram Control Unit

• Execute Instruction

IR ? MPC PC ? PC 4
X ? RegIR2521 Y ? RegIR2016
R ? X Y
RegIR15,11 ? R
µPC M0 S1 S0
C19C18C17C16C15C14C13C12C11C10C9 C8 C7 C6 C5 C4
C3 C2 C1 C0
0 1 1 1 0 1 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0 1
0
1

8
9
1 1
1 0 0
8
1 0 1 0 1 1 0 1
Opcode 0 Funct 100010
0 0 1 0 0 1 0 0 1
54
Chapter 4
The End