The Multicycle Processor II CPSC 321

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The Multicycle Processor IICPSC 321

• Andreas Klappenecker

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Questions? Problems?
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Todays Menu

• The Multicycle Processor
• Introduction to Verilog

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Multicycle Approach

• Single memory unit for instructions and data
• Single arithmetic-logical unit
• Registers after every major unit
• (some visible to the programmer, some not)
• hold output of that unit until value is used in
  next clock cycle
• data used in subsequent instructions must be
  stored in programmer visible registers

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Multicycle Datapath and Control Lines
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Multicycle Datapath and Control Lines
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Instruction Fetch/Decode/Execute
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3rd Step R-Type Instruction
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3rd Step Memory Reference InstructionsMemory
Access
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4th Step Memory Reference InstructionsMemory
Address Computation
Store
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What Happened So Far?

• Single-cycle processor
• Multi-cycle processor
• Next
• Pipelined processor
• Build your own processor _at_ home!

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Verilog
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Levels of Abstraction

• Specification
• Architectural Description
• Verilog, VHDL, ELLA or other HDLs
• Logic Design
• Gates and Registers
• Circuit Design
• Transistors sized for power and speed
• Technology mapping
• Layout

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Levels of Abstraction

• System
• Module
• Gate
• Circuits
• Device

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MOS Transistors

• PMOS transistor
• like a switch
• ON if gate is 1
• OFF if gate is 0
• NMOS transistor
• OFF if gate is 1
• ON if gate is 0

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CMOS Circuits

• Simple
• Avoids difficulties
• Resilient
• Energy efficient
• Current flow only during switching time

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Circuit Design
Layout
Layering and Fabrication
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Hardware Description Languages

• Abstracting from circuits
• Structural description
• Specify full adder by NAND and NOR gates
• Behavioral description
• Specify full adder by functional behavior
• Improves productivity
• Natural for Computer Scientists

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Verilog

• Structural description
• Gates, wires, input/output
• Hierarchical description possible
• (define full adder in terms of gates)
• Behavioral description
• Abstract formulation
• Functional relationships

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Structural Verilog Example
module mux(f, a,b,sel) output f input
a,b,sel wire f1, f2 not(nsel,
sel) and(f1, a,nsel) and(f2, b, sel) or (f,
f1, f2) endmodule
b
f
a
sel
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Behavioral Verilog Example

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• assign f (a sel) (b sel)
• endmodule

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Another Example

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• reg f
• always _at_(a or b or sel)
• if (sel1)
• f b
• else
• f a
• endmodule

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Synthesis

• Compilation
• Verilog code is translated into
• a network of logic gates
• Optimization
• Try to find a better solution by logic
  optimization (limited success)
• Technology mapping
• Physical design

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Logic Gates

• and(y, a, b)
• or(y, a, b)
• not(y, a)
• xor(y, a,b)
• nand(y, a, b)

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Modules

• module mod_name (parameters)
• input
• output
• reg
• endmodule

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Full Adder

• module fulladd(cin, x, y, s, cout)
• input cin, x, y
• output s, cout
• assign s x y cin
• assign cout (x y) (cin x) (cin y)
• endmodule

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Full Adder

• module fulladd(cin, x,y,s, cout)
• input cin, x, y
• output s, cout
• assign cout, s x y cin
• Endmodule
• The assign statement sets cout to MSB and s to LSB

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Verilog Simulators

• vcs from Synopsis
• powerful debugging tools
• Icarus Verilog
• compiler, free
• Veriwell
• simulator, free

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Information about Verilog

• Short manual
• by Chauhan and Blair
• Verilog Quick Reference Guide
• by Sutherland HDL
• Appendix A in Fundamentals of Digital Logic by
  Brown and Vranesic
• Quick Reference for Verilog HDL
• by Rajeev Madhavan

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Hello World

• module top
• initial
• display("Hello, world!")
• endmodule
• initial statements are executed once by the
  simulator

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Verilog Simulator

• The Verilog simulator is event driven
• Different styles of Verilog
• structural
• dataflow
• behavioral
• We will see examples of each type

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Nets

• A net represents a node in the circuit
• The wire type connects an
• output of one element to an
• input of another element
• wire abar
• not(abar, a)
• nand(b, abar,abar)

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Vector wires

• Range msb lsb
• wire 30 S
• S 4b0011
• The result of this assignment is
• S3 0, S2 0, S1 1, S0 1
• wire 12 A
• A S21
• means A1 S2, A2 S1

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Variables

• Variables come in two flavors
• reg
• integers
• reg can model combinatorial or sequential parts
  of the circuits
• reg does not necessarily denote a register!
• Integers often used as loop control variables
• useful for describing the behavior of a module

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Simple Example

• module testgate
• reg b, c // variables
• wire a, d, e // nets
• and (d, b, c) // gates
• or (e, d, c) //
• nand(a, e, b) //
• initial begin // simulated once
• b1 c0 // blocking assignments
• 10 display("a b", a)
• end
• endmodule What value will be printed?

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Operators

• 1s complement A
• 2s complement -A
• bitwise AND AB
• reduction A produces AND of all bits in A
• Concatenate a,b,c
• a,b,c a b c
• Replication operators 2A A,A
• 2A,3B A,A,B,B,B

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Continuous assignments

• Single bit assignments
• assign s x y cin
• assign cout (x y) (cin x) (cin y )
• Multibit assignments
• wire 13 a,b,c
• assign c a b

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Full Adder

• module fulladd(cin, x, y, s, cout)
• input cin, x, y
• output s, cout
• assign s x y cin
• assign cout (x y) (cin x) (cin y)
• endmodule

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Always Blocks

• An always block contains one or more procedural
  statements
• always _at_(sensitivity list)
• always _at_(x or y)
• begin
• s x y
• c x y
• end

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Mux Structural Verilog
module mux(f, a,b,sel) input a,b,sel
output f wire f1, f2 not(nsel, sel)
and(f1, a,nsel) and(f2, b, sel) or (f, f1,
f2) endmodule
b
f
a
sel
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Conclusion

• Verilog abstracts hardware
• Modules represent hardware units
• You can specify the behavior in
• structural
• dataflow-oriented
• behavioral
• ways.

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Mux Dataflow Model

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• assign f (a sel) (b sel)
• endmodule

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Mux Behavioral Model

• module mux2(f, a,b,sel)
• output f
• input a,b,sel
• reg f
• always _at_(a or b or sel)
• if (sel1)
• f b
• else
• f a
• endmodule