Multicycle Datapath

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Multicycle Datapath Control

• Andreas Klappenecker
• CPSC321 Computer Architecture

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Administrative Issues

• Office hours have been moved
• Today canceled
• Thursday 200pm-300pm
• Seek help if you did not do well on the test
• Lab 3 due next week

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Multi-Cycle Processor
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Multicycle Approach

• Single memory unit for
• instructions
• data
• Single ALU
• Registers after every major functional unit
• hold output of that unit until value is used in
  next clock cycle
• data used in subsequent instructions must be
  stored in programmer visible registers

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Multicycle Datapath
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Additional Internal Registers

• Instruction and memory data register
• both memory and instruction registers are used
  because both values are needed
• A and B registers
• hold register operands
• ALUout register
• holds output of ALU

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Five Execution Steps

• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch
  Completion
• Memory Access or R-type instruction completion
• Write-back stepINSTRUCTIONS TAKE FROM 3 - 5
  CYCLES!

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Step 1 Instruction Fetch

• Use PC to get instruction and put it in the
  Instruction Register.
• PC PC 4
• RTL "Register-Transfer Language" IR
  MemoryPC PC PC 4What is the advantage
  of updating the PC now?

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Step 2 Instruction Decode and Register Fetch

• Read registers rs and rt in case we need them
• Compute the branch address in case the
  instruction is a branch
• RTL
• A RegIR25-21B RegIR20-16ALUOut
  PC(sign-extended(IR15-0)ltlt2)
• No control lines based on the instruction type
  are set b/c control logic busy "decoding".

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Step 3 (instruction dependent)

• ALU performs one of three functions, based on
  instruction type
• Memory Reference
• ALUOutAsign-extend(IR15-0)
• R-type ALUOut A op B
• Branch if (AB) PC ALUOut

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Step 4 (R-type or memory-access)

• Loads and stores access memory
• MDR MemoryALUOut
• or MemoryALUOut B
• R-type instructions finish RegIR15-11
  ALUOutThe write actually takes place at the
  end of the cycle on the edge

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Write-back step

• Load operations
• RegIR20-16 MDR
• What about all the other instructions?

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Summary
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Clock Cycles per Instruction

• R-type
• 4 clock cycles
• Memory reference instructions
• 5 clock cycles
• Branches
• 3 clock cycles
• Jumps
• 3 clock cycles

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Questions

• How many cycles will it take to execute this
  code? lw t2, 0(t3) lw t3, 4(t3) beq
  t2, t3, Label assume not add t5, t2,
  t3 sw t5, 8(t3)Label ...
• What is going on during the 8th cycle of
  execution?
• In what cycle does the actual addition of t2 and
  t3 takes place?

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MIPS Multicycle Datapath

• Incomplete (branch and jumps)

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Control

• What are the control signals?
• Finite state machine control
• Instruction fetch
• instruction decode
• memory reference
• R-type
• branch
• jump

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Multicycle Datapath and Control Lines
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(No Transcript)
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Outlook

• What happens precisely during each step of
  fetch/decode/execute cycles
• Construct the finite state control machine
• High-level view