CPSC 321 Computer Architecture Designing a Single Cycle Datapath

1
CPSC 321Computer Architecture Designing a
Single Cycle Datapath

• Adapted from the lecture notes of John
  Kubiatowicz(UCB) and Praveen

2
The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Todays Topic Design a Single Cycle Processor

3
The Big Picture The Performance Perspective

• Performance of a machine is determined by
• Instruction count
• Clock cycle time
• Clock cycles per instruction
• Processor design (datapath and control) will
  determine
• Clock cycle time
• Clock cycles per instruction
• Today
• Single cycle processor
• Advantage One clock cycle per instruction
• Disadvantage long cycle time

4
How to Design a Processor step-by-step

• 1. Analyze instruction set gt datapath
  requirements
• the meaning of each instruction is given by the
  register transfers
• datapath must include storage element for ISA
  registers
• possibly more
• datapath must support each register transfer
• 2. Select set of datapath components and
  establish clocking methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic

5
The MIPS Instruction Formats

• All MIPS instructions are 32 bits long. The
  three instruction formats
• R-type
• I-type
• J-type
• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination register
  specifiers
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

6
Step 1a The MIPS-lite Subset for today

• ADD and SUB
• addu rd, rs, rt
• subu rd, rs, rt
• OR Immediate
• ori rt, rs, imm16
• LOAD and STORE Word
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16

7
Logical Register Transfers

• RTL gives the meaning of the instructions
• All start by fetching the instruction

op rs rt rd shamt funct MEM PC op
rs rt Imm16 MEM PC
inst Register Transfers ADDU Rrd lt Rrs
Rrt PC lt PC 4 SUBU Rrd lt Rrs
Rrt PC lt PC 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 LOAD Rrt lt MEM
Rrs sign_ext(Imm16) PC lt PC 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrt PC lt PC
4 BEQ if ( Rrs
Rrt ) then PC lt PC 4 sign_ext(Imm16)
00
else PC lt PC 4
8
Step 1 Requirements of the Instruction Set

• Memory
• instruction data
• Registers (32 x 32)
• read RS
• read RT
• Write RT or RD
• PC
• Extender
• Add and Sub register or extended immediate
• Add 4 or extended immediate to PC

9
Step 2 Components of the Datapath

• Combinational Elements
• Storage Elements
• Clocking methodology

10
Combinational Logic Elements (Basic Building
Blocks)
CarryIn

• Adder
• MUX
• ALU

A
32
Sum
Adder
32
B
Carry
32
Select
A
32
Y
MUX
32
B
32
OP
A
32
Result
ALU
32
B
32
11
Storage Element Register (Basic Building Block)
Write Enable

• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable
• negated (0) Data Out will not change
• asserted (1) Data Out will become Data In

Data In
Data Out
N
N
Clk
12
Storage Element Register File
RW
RA
RB

• Register File consists of 32 registers
• Two 32-bit output busses
• busA and busB
• One 32-bit input bus busW
• Register is selected by
• RA (number) selects the register to put on busA
  (data)
• RB (number) selects the register to put on busB
  (data)
• RW (number) selects the register to be
  writtenvia busW (data) when Write Enable is 1
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a combinational
  logic block
• RA or RB valid gt busA or busB valid after
  access time.

Write Enable
5
5
5
busA
busW
32
32 32-bit Registers
32
busB
Clk
32
13
Storage Element Idealized Memory
Write Enable
Address

• Memory (idealized)
• One input bus Data In
• One output bus Data Out
• Memory word is selected by
• Address selects the word to put on Data Out
• Write Enable 1 address selects the memoryword
  to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a
  combinational logic block
• Address valid gt Data Out valid after access
  time.

Data In
DataOut
32
32
Clk
14
Clocking Methodology
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge
• Cycle Time CLK-to-Q Longest Delay Path
  Setup Clock Skew
• (CLK-to-Q Shortest Delay Path - Clock Skew) gt
  Hold Time

15
Step 3 Assemble Datapath meeting our requirements

• Register Transfer Requirements ? Datapath
  Assembly
• Instruction Fetch
• Read Operands and Execute Operation

16
3a Overview of the Instruction Fetch Unit

• The common RTL operations
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Clk
PC
Instruction Word
32
17
3b Add Subtract

• Rrd lt- Rrs op Rrt Example addu rd,
  rs, rt
• Ra, Rb, and Rw come from instructions rs, rt,
  and rd fields
• ALUctr and RegWr control logic after decoding
  the instruction

Rs
Rt
Rd
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
18
Register-Register Timing One complete cycle
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA, B
Old Value
New Value
ALU Delay
busW
Old Value
New Value
Rs
Rt
Rd
ALUctr
Register Write Occurs Here
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
19
3c Logical Operations with Immediate

• Rrt lt- Rrs op ZeroExtimm16

Rt?
Rs
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
Clk
busB
32
Mux
ZeroExt
imm16
32
16
ALUSrc
20
3d Load Operations

• Rrt lt- MemRrs SignExtimm16 Example lw
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Rt?
Rs
ALUctr
RegWr
5
5
5
busA
W_Src
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
MemWr
32
Mux
Mux
WrEn
Adr
Data In
32
??
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc
ExtOp
21
3e Store Operations

• Mem Rrs SignExtimm16 lt- Rrt Example
  sw rt, rs, imm16

22
3f The Branch Instruction

• beq rs, rt, imm16
• memPC Fetch the instruction from memory
• Equal lt- Rrs Rrt Calculate the branch
  condition
• if (Equal) Calculate the next instructions
  address
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• else
• PC lt- PC 4

23
Datapath for Branch Operations

• beq rs, rt, imm16 Datapath generates
  condition (equal)

Inst Address
nPC_sel
32
00
imm16
PC Ext
24
Putting it All Together A Single Cycle Datapath
Instructionlt310gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Equal
Rt
Rd
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb

busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Extender
Data Memory
imm16
PC Ext
32
Clk
16
Clk
imm16
ExtOp
ALUSrc
25
An Abstract View of the Critical Path

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
26
An Abstract View of the Implementation
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Datapath
27
Recap A Single Cycle Datapath

• Rs, Rt, Rd and Imed16 hardwired into datapath
  from Fetch Unit
• We have everything except control signals
  (underline)
• Todays lecture will show you how to generate the
  control signals

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr
ALUctr
5
5
5
Zero
MemtoReg
MemWr
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
28
Recap Meaning of the Control Signals

• nPC_MUX_sel 0 ? PC lt PC 4 1 ? PC lt PC
  4 SignExt(Im16) 00
• Later in lecture higher-level connection between
  mux and branch cond

29
Recap Meaning of the Control Signals

• MemWr 1 ? write memory
• MemtoReg 0 ? ALU 1 ? Mem
• RegDst 0 ? rt 1 ? rd
• RegWr 1 ? write register

• ExtOp zero, sign
• ALUsrc 0 ? regB 1 ? immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
0
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
Data In
1
Extender
Data Memory
imm16
32
16
Clk
ExtOp
ALUSrc
30
RTL The Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

31
Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory
  Instruction lt- memPC
• This is the same for all instructions

Instructionlt310gt
nPC_MUX_sel
4
00
PC
Clk
imm16
PC Ext
32
The Single Cycle Datapath during Add

• Rrd lt- Rrs Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 1
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
33
Instruction Fetch Unit at the End of Add

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

Instructionlt310gt
nPC_MUX_sel
4
0
00
PC
1
Clk
imm16
34
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
35
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
36
The Single Cycle Datapath during Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
37
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
38
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
32
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
39
The Single Cycle Datapath during Branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

Instructionlt310gt
nPC_sel Br
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Sub
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
40
Instruction Fetch Unit at the End of Branch

• if (Zero 1) then PC PC 4
  SignExtimm164 else PC PC 4

Instructionlt310gt
nPC_sel
Zero

• What is encoding of nPC_sel?
• Direct MUX select?
• Branch / not branch
• Lets choose second option

nPC_MUX_sel
4
0
00
PC
1
Clk
imm16
41
Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
ALUSrc
RegDst
ExtOp
RegWr
Zero
nPC_sel
DATA PATH
42
A Summary of Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel Br, ALUctr sub
43
A Summary of the Control Signals
func
100000
See
100010
We Dont Care -)
Appendix A
op
000000
000000
001101
100011
101011
000100
000010
44
The Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
45
The Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop has to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, and (5) And
  (Example andi)

46
The Decoding of the func Field
47
The Truth Table for ALUctr
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
48
The Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
This makes funclt3gt a dont care

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

49
The Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt !
  ALUoplt2gt ALUoplt1gt ALUoplt0gt ALUoplt2gt
  !funclt2gt !funclt0gt

50
The Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

51
The ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

52
Step 5 Logic for each control signal

• nPC_sel lt (OP BEQ) ? Br plus4
• ALUsrc lt (OP Rtype) ? regB immed
• ALUctr lt (OP Rtype) ? funct (OP
  ORi) ? ORfunction (OP BEQ) ?
  SUBfunction ADDfunction
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

53
Step 5 Logic for each control signal

• nPC_sel lt (OP BEQ) ? Br plus4
• ALUsrc lt (OP Rtype) ? regB immed
• ALUctr lt (OP Rtype) ? funct (OP
  ORi) ? ORfunction (OP BEQ) ?
  SUBfunction ADDfunction
• ExtOp lt (OP ORi) ZEROextend
  SIGNextend
• MemWr lt (OP Store) ? 1 0
• MemtoReg lt (OP Load) ? 1 0
• RegWr lt ((OP Store) (OP BEQ)) ? 0
  1
• RegDst lt ((OP Load) (OP ORi)) ? 0
  1

54
The Truth Table for the Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
nPC_sel
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
55
The Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
0
0
0

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
56
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
57
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
Instrlt50gt
6
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
58
Recap An Abstract View of the Critical Path
(Load)

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
59
Worst Case Timing (Load)
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
MemtoReg
Old Value
New Value
Register Write Occurs
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
60
Drawback of this Single Cycle Processor

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time for load is much longer than needed
  for all other instructions

61
Preview

• Next Time
• MultiCycle Data Path
• CPI ? 1, CycleTime much shorter (1/5 of time)

62
Summary

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

Processor
Input
Control
Memory
Output