Processor Design

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Processor Design

• Datapath and Design

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All tables and diagrams in this presentation are
from

• D. Patterson and J. Hennessy, Computer
  Organization and Design The Hardware/Software
  Interface, Third Edition (The Morgan Kaufmann
  Series in Computer Architecture and Design),
  Morgan Kaufmann, 2002.

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Datapath
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Basic Functional Units
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Instruction Sequencing
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Operations on Data in Registers
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Registers and Memory
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Simple Implementation Scheme

• Single cycle Implementation

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ALU Conttrol
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Control Signals
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R-format and I-format Instructions
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Control Signals and Instruction Opcode
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Control Function
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Multicycle Implementation
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Intstruction fetch IR lt MemoryPC PC lt PC4
IR lt MemoryPC
PC lt PC4
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IorD 0
MemRead 1
IRWrite 1
IR lt MemoryPC
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PCSource 01
PCWrite 1
ALUOp 00
ALUSrcB 01
ALUSrcA 0
PC lt PC4
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Intstruction decode/register fetch A lt Reg IR
2521 B lt Reg IR 2016 ALUOut lt PC
( SignExt( IR150 ) ltlt 2 )
A lt Reg IR 2521 B lt Reg IR 2016
ALUOut lt PC ( SignExt( IR150 ) ltlt 2 )
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A lt Reg IR 2521 B lt Reg IR 2016
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ALUOp 00
ALUSrcB 11
ALUSrcA 0
ALUOut lt PC ( SignExt( IR150 ) ltlt 2 )
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R-type instruction ALUOut lt A op B Reg
IR1511 lt ALUOut
ALUOut lt A op B
Reg IR1511 lt ALUOut
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ALUOp ??
ALUSrcB 0
ALUSrcA 1
ALUOut lt A op B
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RegWrite 1
MemtoReg 0
RegDst 1
Reg IR1511 lt ALUOut
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Load instruction ALUOut lt A SignExt(IR150) M
DR lt MemoryALUOUT RegIR2016 lt MDR
ALUOut lt A SignExt(IR150)
MDR lt MemoryALUOUT RegIR2016 lt MDR
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ALUOp 00
ALUSrcB 10
ALUSrcA 1
ALUOut lt A SignExt(IR150)
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IorD 1
MemRead 1
RegWrite 1
MemtoReg 1
RegDst 0
MDR lt MemoryALUOUT RegIR2016 lt MDR
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