GOL

1
GOLFPGA remake

• Annie Xiang
• Fall, 2006

2
GOL field requirement

• 1mm thickness on the edge a must
• 50mmx150mm, could be longer
• Minimize metal (jumpers, SMAs)

3
Xilinx vs Altera FPGAs

• Each board need to control gt2 channels
• LVDS IOs
• Quad package over BGAs

4
Xilinx vs Altera FPGAs

• 622Mb/s, 260MHz
• HSTL, LVDS, LVPECL, LVCMOS, LVTTL

5
GOL measurement plan

• Flux, fluence
• TID error free -10KeV Xray, 10Krad(SiO2)/min to
  10Mrad
• SEU not seen - 60MeV proton, 3x10e8 p/cm2.sec
• Note that at 3.5e8 p/cm2sec for 50min, 130Krad,
  TLK will incur 8-11 SEU
• Run-time equivalent