Introduction to Xilinx CPLDs

1
Introduction to Xilinx CPLDs
2
Agenda

• CPLD Introduction
• XC9500 Family Overview
• CoolRunner XPLA3 Overview
• CoolRunner-II Overview
• IQ Products for Automotive and Industrial
• Software Updates and Online Support
• Customer Success Stories

3
Complex Programmable Logic Device
interconnect
macrocells
macrocells
A hybrid of PLD blocks interconnect for
mid-size logic designs
4
CPLD Design Flow
Specification
libraries
HDL
Gates of the design ...
netlist
CPLD Design Flow
Verification

test vectors
Implementation
Translate
Fitting
... are fitted to the CPLD
Download/ Program
device
System Debug
printed circuitboard
5
High Performance

• Pin-to-Pin combinatorial delay
• Time from input, thru interconnect to output (ns)

• Maximum registered frequency
• Fastest operation of flip-flops (MHz)

CPLD
Macrocell
fMAX (MHz)
6
Wide Package Offering

• High pin count package for lots of I/Os
• Maximum logic with minimal I/Os
• Logic consolidation for space (vs. discrete
  devices)
• Lower cost packaging

A smaller CPLD package means a smaller board!
7
CPLD Voltage Integration 5v, 3.3v, 2.5v, 1.8v
and 1.5v

• 3.3v 2.5v is the current market trend moving to
  1.8v and below for portable and low power
  applications
• Cost reduction to eliminate 5v supply and
  regulators with 5v tolerance
• Some components will not migrate to 3.3v or below
• Need to interface with 3.3v, 2.5V, 1,8v and/or
  1.5v components

5v
5v
5v
5v
5v
3.3v
1.5v
1.8v
2.5v
3.3v CPLD required to interface with 5v, 3.3v
2.5v components 2.5v CPLD required to interface
with 3.3v, 2.5v 1.8v components 1.8v CPLD
required to interface with 3.3v, 2.5v, 1,8v
1.5v components
8
System Integration Advantage
9
System Level Savings

• High volume economies of scale
• Single chip for multiple system solutions
• Increase volume means reduction in all related
  costs
• Reference designs
• Minimize risk and shorten design cycle
• Lowest cost per I/O
• Examples include
• On The Fly (OTF) reconfiguration
• Two devices for the price of one

10
Designers Need Low Power

• Longer lasting battery life
• Lower overall system cost (eliminate fans/ reduce
  power supplies)
• Increased system reliability
• Fits into hand-held applications

11
CPLD Advantage over Discrete Logic
XPLATM Architecture
Equivalent to
TQFP 100
XCR3128XL
Or XCR3064 XL 3.3V parts in the same
package bridging two densities for added design
flexibility
Real design example Aircraft Passenger Handset -
Smaller PCB with less layers (lower cost) - 7 to
3 layers! - One part to purchase stock, less
inventory - One part to pick and place in
manufacture, saving time - Design can be
changed and enhanced without PCB re-layout -
even in the field - Stock and purchase one part
instead of 17 in this example!
12
Xilinx CPLDHigh Volume Shipments
Units Shipped

• Xilinx currently ships gt10M CPLD units per Qtr
• WW CPLD market share growing at gt1 per Qtr

13
CPLD Product Portfolio

• 3.3V core
• 2.7V - 5V I/O
• LVCMOS, LVTTL
• Low power
• Fast Zero Power

• 1.8V RealDigital core
• 1.5V - 3.3V I/O
• SSTL, HSTL, LVCMOS, LVTTL
• Lower power
• DataGATE
• Clocking features
• Clock Divide
• CoolCLOCK
• DualEDGE
• I/O banking

• 2.5V core
• 1.8V - 3.3V I/O
• LVCMOS, LVTTL
• I/O banking

• 3.3V core
• 2.5V - 5.0V I/O
• LVCMOS, LVTTL

14
Quick Design Capability with CPLDs
15
Product Lifetime Dynamics
Units
Cellular
Target high volume, short production life
applications
PDA
PC
Games
TV
1
2
Years in Production
New products stay in volume for shorter periods,
Time To Market is critical!
16
ASIC Development Take Too Long!

• Product life cycles maybe shorter than ASIC
  development time
• Multiple ASIC spins may miss the market window
• Smaller than expected run rates may not justify
  the ASIC development cost
• Long ASIC development times do not allow last
  minute design revision changes
• Revisions leave little time to run in production
• Programmable logic allow customers to address
  market changes quicker

17
ASICs Give Designers Only ONE Chance
Freeze design here
No chance for last minute design changes
ASIC
Spec
Design Verification
System Integration
Silicon Prototype
Silicon Production
First Ship
Re-programming allows last minute design changes
CPLD
Spec
System Integration
First Ship
Design Verification
Freeze design here

• CPLD flexibility allow performance analysis and
  late HW/SW changes meeting customer needs and
  improves Time To Market with faster, lower risk
  designs

18
CoolRunner Reference Designs

• Shorten design cycle time
• Eliminate code porting costs for next design
  cycle
• Re-use of HDL is reliable and stable
• Minimize design risk by using reference designs
• Availability of reference designs prepares you
  for unexpected system changes
• Update main processor but it does not incorporate
  correct bus interface
• Further improve customers Time To Market
• Proven designs for quick turn requirements

19
Faster Designs with FREECoolRunner Reference
Designs
Coming soon
Free VHDL design code www.xilinx.com/products/xaw
/coolvhdlq.htm
20
CoolRunner-II Design Kit
21
Development Board Cable Support
Note There may be regional variations because of
different mains voltages - check locally for full
part number
22
CPLD Software Improvements in 6.1

• Ease of use
• Improved CPLD process flow
• Single process (Implement Design) will pull the
  design through the entire fitting process
• Granular control still possible for power users
  by expanding individual processes
• New design creation aids
• New project wizard leads the user through the
  project creation process
• Add existing source / Create new source processes
  - assist in getting started faster
• Centralized process properties menu
• Web Update
• Built in utility checks for service packs and
  supplemental CPLD updates
• Downloads and installs update in single step

XC9500XL / XV Product Overview
File Number Here
23
Xilinx CPLD Process Leadership
Year used in
SPLD/CPLD
Year used in

• Non-Volatile

Technology
Memories
SPLD/CPLD
Pioneer
Bipolar Fuse
1973
1978
MMI (AMD)
EPROM
1979
1984
Altera EP-series
5V EEPROM
1986
1991
Lattice ispLSI
5V FLASH
1990
1995
Xilinx XC9500
3.3V FLASH
1993
1998
Xilinx XC9500XL
2.5V FLASH
1996
2000
Xilinx XC9500XV
24
Higher Voltage CPLD Solutions To Fit Every Need

• 5 / 3.3 / 2.5V core
• 36-288 macrocells
• High Performance
• Superior pin-locking
• Low cost

XC9500 Families
XC9500
XC9500XL
XC9500XV
2.5V core
5V core
3.3V core
25
XC9500/XL/XV Family FeaturesOverview
CPLD Designer Needs

• High fMAX 278 MHz
• Fast TPD 3.5nS
• Instant productivity software tools
• Best pin-locking capability
• Best ISP/JTAG support
• Support for all ATE manufacturers
• Advanced packaging including CSP
• XC9500XL for 3.3v (5v tolerant 2.5v I/O)
• XCR9500XV for 2.5v (1.8v 3.3v I/O)
• Best CPLD pricing in the industry!

High Performance Time to Market Fit in
Existing Flow Package offering 5v,3.3v 2.5v
Lowest cost
26
XC9500XL / XV Families
27
XC9500 5V Family
XC9536
XC9572
XC95108
XC95144
XC95216
XC95288
36
72
108
144
Macrocells
216
288
Usable Gates
800
1600
2400
3200
6400
4800
5
7.5
7.5
7.5
15
tPD (ns)
10
36
72
108
144
288
Registers
216
Max. User I/Os
34
72
108
133
192
166
44VQ 44PC 48CSP
44PC 84PC 100TQ 100PQ
84PC 100TQ 100PQ 160PQ
100TQ 100PQ 160PQ
Packages
208HQ 352BG
160PQ 208HQ 352BG
28
XC9500 5V Family
XC9536
XC9572
XC95108
XC95144
XC95216
XC95288
36
72
108
144
Macrocells
216
288
Usable Gates
4800
800
1600
2400
3200
6400
10
5
7.5
7.5
7.5
15
TPD (ns)
36
72
108
144
216
288
Registers
Max. User I/Os
34
72
108
133
166
192
Packages
44VQ 44PC 48CS
44PC 84PC 100TQ 100PQ
84PC 100TQ 100PQ 160PQ
100TQ 100PQ 160PQ
208HQ 352BG
160PQ 208HQ 352BG
29
XC9500XL 3.3V Family
30
XC9500XV 2.5V Family
31
XC9500/XL/XV Family Features Driving the ISP
Revolution

• Complete support of ISP designers Product Life
  Cycle
• Provides industrys best pin-locking CPLD at
  lowest price
• Complete state-of-the-art software support
• CPLDs key part of the Xilinx total logic
  solution
• Benefits of ISP
• No need for costly device programmers, fewer
  board re-spins, less scrap and re-work, reduces
  design and development time scales, enables field
  upgrades, eliminates unnecessary package
  handling,

x
Program the whole board not each chip!
32
XC9500/XL/XV Family Features Most Complete JTAG
Testability

• IEEE Std 1149.1 boundary-scan
• Testability advanced system debug/diagnosis
• 8 instructions supported (incl. CLAMP)
• Full support on all family members
• 1532 Industry-standard ISP interface
• Complete 3rd party support
• Benefits of JTAG Improved testability, higher
  system reliability, cheaper test equipment,
  shorter test time, reduced spare board
  inventories, reduces device handling.

33
XC9500/XL/XV Family Features Innovative CSP
Packaging

• New 48-pin Chip Scale Package (CSP)
• 1/3 size VQFP-44, 82 smaller than PLCC-44
• Big board space benefits
• New 144-pin CSP (117 user I/Os)
• Uses standard IR surface mounting process
• Supports industrys high growth market segments
• Communications, Computers, Consumer

PC44 5.6X
34
XC9500/XL/XV Family FeaturesNew price points
open up new apps

• Motherboards for PCs and servers
• PC peripherals and add-on cards
• DVD players/controller cards
• Graphics cards
• Automotive
• Engine control
• Automotive navigation systems (GPS)
• Consumer
• LAN / DSLAM
• Video Games/Toys

35
CPLD Software Improvements in 6.1

• Ease of use
• Improved CPLD process flow
• Single process (Implement Design) will pull the
  design through the entire fitting process
• Granular control still possible for power users
  by expanding individual processes
• New design creation aids
• New project wizard leads the user through the
  project creation process
• Add existing source / Create new source processes
  - assist in getting started faster
• Centralized process properties menu
• Web Update
• Built in utility checks for service packs and
  supplemental CPLD updates
• Downloads and installs update in single step

CoolRunner XPLA3 Product Overview
File Number Here
36
XCR3000XL Family FeaturesOverview

• High fMAX 200MHz
• Fast TPD 5nS
• Instant productivity software tools
• Best ISP/JTAG support
• Worlds Smallest BGAs (CP56)
• Industrys 1st most efficient architecture -
  PLA
• Ultra low power operation
• No power/performance tradeoffs
• Low Power High Reliability

CPLD Designer Needs
High Performance Time to Market Package
offering Low power
THESE PARTS ARE FOR LOW POWER APPLICATIONS!
37
CoolRunner XPLA3 Family
38
XCR3000XL Family Features Low Power

• Dynamic Battery Life
• Populated with 16 bit counters _at_ 20MHz
• 2 AA batteries
• Non CoolRunner devices in low power mode

Competitive Device Families
3.3V CPLD Low Power Leadership!
39
XCR3000XL Family Features Extra Hidden
Benefits of Low Power

• Eliminates Expensive Heat Sinks Cooling Fans
• Heat Sinks 0.50 - 12.00
• Fans 3.50 and up
• Decreases Power supply component size for
• High Performance
• Small Portable Form Factors
• Computing Lap Palm Enclosures
• Higher product density

Less Heat Higher Performance, Cost Savings
Reliability!
40
Thermal Emissions Comparison

• Devices programmed with 16 bit counters with the
  MSB brought out to an LED and operated at 50MHz
• Where applicable, competitive devices were in
  non-turbo mode
• Note the MACH4 device is 128 macrocells, Lattice
  is 192 macrocells (largest in the family)

41
Thermal Characteristics
The Altera MAX3000A 256 macrocell device was
powered up in low power mode and loaded with a 16
bit counter and clocked at 50MHz. A thermal
imaging camera measured the Altera device (P1) to
be _at_ 40.23ºC, (P2) was a CoolRunner XCR3256XL
device _at_ 30.03ºC, the back ground temperature was
22.88ºC (P3)
42
Higher System Reliability

• Activation Energy EA Aggravated by Temperature!

• Increased Temperature Decreased Reliability

43
Lower Power Smaller Packages

• XPLA3 supports small industry standard packages
• New Chip Scale Packaging
• CS48
• CP56

44
The RealDigital CPLD A New Class of CPLD
with High Performance and Ultra Low Power without
Compromise!
45
CPLD Sense amp Designs Have Migration Limits
Sense amp based CPLD technologies dont scale
effectively beyond 0.18µ
46
High Level Architecture
47
Function Block Architecture
48
Logic Allocation Advantage
PAL Requires 4 product terms!
PLA Requires only 3 product terms!
C
B
A
Can NOT share common logic
X A B C Y A B !C
Y
X
Common logic may be shared in CoolRunner-II
49
Macrocell Architecture
FB Inputsfrom AIM
application notes http//www.xilinx.com/apps/epld
.htm
40
PLA Array
49 P terms
Macrocell
4 Control Terms
from I/O Block (Fast Input)
Feedback to AIM
PTA
PTB
VCC
PTC
GND
S
Q
D/T
FIF
Latch
DualEDGE
CE
PTC
GCK0
GCK1
CK
R
GCK2
CTC
PTC
50
I/O Block Characteristics
VREF for Local Bank
HSTL SSTL
VCCIO
VREF
to AIM
128 macrocell and larger devices
Input Hysteresis
to Macrocell (Fast Input)
3.3V - 1.5V Input
VCCIO
Slewrate
from Macrocell
Enabled
Control Term
PTB
/
4
GTS03
CGND
Open Drain
Disabled
51
I/O Flexibility
Note 1.5v inputs need hysteresis
52
RealDigital Design Advantage
Turbo vs Non Turbo Larger R slower response
less power
Vcc
A
B
C
Sense amplifier 0.25mA each - Standby Higher ICC
at Fmax

• Traditional CPLDs - bipolar sense amp product
  terms
• Always consumes power
• Even at standby
• Performance is traded for power consumption as
  devices get larger

• CoolRunner-II RealDigital design uses 100 CMOS
  for product terms
• Virtually no standby current
• Combines high performance ultra low power
• No power limits on device size

53
Reducing Power

• Icc C x V x f
• To reduce power
• Lower capacitance
• Lower voltage
• Lower frequency

• 0.18 m lowers capacitance
• Low VCC _at_ 1.8V
• How can we reduce the frequency?

54
Low Power CPLDs

• CoolRunner XPLA3
• Low power
• 3.3V core with 5V tolerance
• CoolRunner II
• Ultra Low Power
• Lowest Cost
• Feature Rich
• 1.8V core with 1.5v to 3.3V compatibility

And our parts still run on GRAPEFRUIT!
55
Beware! Not all Low Power Logic is Created
Equal!

• Some logic devices have power down modes
• Complicates timing models (non-deterministic)
• Power down modes slow timing (TPD / Fmax) when
  used
• Some logic devices shut down when not active
• Latency periods apply for wakeup (typ. 50ns)
• No power savings when operating
• Choose Logic to simplify design process
• No speed / power tradeoffs
• Simple timing models

56
500mV Input Hysteresis

• Supports simple oscillation schemes
• Ideal for slow edge rate, noisy signals
• Analog comparators sensors
• Hall effect switches
• IR inputs
• R/C oscillators
• Eliminate external Schmitt trigger buffers
• Reduces power consumption with slow signals

V
CoolRunner-II
_
In

CoolRunner-II
57
Solving Signal Integrity Challenges

• Noisy, slow analog signals
• Hall Sensor
• R/C Oscillator
• XTAL input
• RFI, EMI effects

Input hysteresis

• With input hysteresis
• Analog signals function as digital inputs
• Saves power by non-linear operation
• Added noise immunity

58
DualEDGEPerformance Enhancing

• In all CoolRunner-II devices
• Edge detect doubles clock up to 500MHz
• Selectable on a per macrocell basis
• Ideal for Double Data Rate (DDR) memory
• devices

59
Clock Divider Power Efficient

• 128, 256, 384 512 macrocell
• 2,4,6,8,10,12,14 or 16 digital clock divide
• Reduce external oscillators
• 50 duty cycle
• Reduces cross talk

Divide by 4
60
CoolCLOCK

• Further power reduction plus performance
• Combination of clock divider DualEDGE (clock
  doubler)
• Divide incoming clock by two (lowing total
  power), then double at macrocell for high speed
  requirements

CPLD
Global
Macrocell
Divider
Input
Divide by 2
Doubler
Original frequency
Output
61
DataGATE

• Another low power enhancement
• Control DataGATE signal externally or internally
• User programmable on/off switch for specific
  inputs
• Only enable inputs when necessary
• Great for power reduction on wide logic
  interfaces
• Latch data when valid, reduces unnecessary signal
  toggling

DataGATE Diagram
DataGATE control signal
Gated internal signal
Input pin
62
The Best Design Security
Easy To Use
New Capabilities

• 1532 in system programming
• 1149.1 JTAG boundary scan
• Fast Programming times

• Multiple levels of security
• Affect different mechanisms
• Interconnects are buried
• Multiple security signals
• Scattered and layered

Xilinx WebPACKor Foundation ISE Software
63
RealDigital CPLD Advantage
64
Chip Scale Packaging Leadership
17.6 mm
44 PLCC
12 mm
44 VQFP
8 mm
17.6 mm
132 CP
12 mm
56 CP
8 mm
Supports high-growth market segments
Communications, Computers, Consumer, especially
wireless
6 mm
6 mm
Uses standard IR techniques for mounting to PC
board
65
Lower Power Smaller Packages

• 56-Ball 0.5mm CSP
• Provides 44 I/Os
• 0.5mm pitch
• 36 mm2 footprint
• Ideal for handheld portable applications
• PDAs
• Portable PCs
• Cellular Phones
• Telecom Networking Equipment
• Network Appliances

66
Best Package Offering for High Volume Applications
CP56 (6 x 6mm)
Smallest form factor chip scale packages

• Optimized packaging
• Smallest size chip scale
• Highest performance BGA
• Highest I/O count
• Small size
• Lowest cost flat pack

CP132 (8 x 8mm)
VQ44 (10 x 10mm)
VQ100 (14 x 14mm)
FT256 (17 x 17mm)
PC44 (16.5 x 16.5mm)
Small form factor, highest performance, BGA
packages
TQ144 (20 x 20mm)
FG324 (23 x 23mm)
PQ208 (28 x 28mm)
Package widths drawn to scale.
67
CoolRunner-II Family Overview
68
PDA CoolRunner Reference Design Example
Battery
Compact Flash
SMBus
IrDA
LED
?P
UART
Docking Cradle
LCD
SPI
Indicates a CoolCORE
69
Exploiting Our Technology Lead
0.35 0.25 0.18 0.13 0.09 0.07
CPLDs
Feature Size (micron)
Clipper
FPGAs
Schooner
2000 2001
2002 2003
2004 2005
70
XCR3000XL XC2C Low Power Features Open Up New
Applications
Telecom Neighborhood Multiplexors Bay
Stations Routers Multiplexors PBXs WLAN Central
office switches Speech recognition systems PC
Peripheral PCMCIA cards Portable computer
displays White board scanners Memory cards High
Performance Workstations and servers Video
graphics cards Storage Systems
Portable / Consumer PDAs Cell phones MP3
players Laptops Docking stations Battery powered
scanners PDA add-on modules Digital
cameras Portable dictation systems Gas
meters Handheld meters Smart Card
Readers Payphones Medical Portable syringe
pump Home monitoring system Blood analyzer
71
One Ultimate CPLD Solution for All Designs
Lowest Power 9.9mW 16µA typical stand-by
Low Cost 0.18µ small die size Lowest cost
packaging
High Performance 3.0ns TPD, FMAX 385Mhz Improved
features
Storage Systems, Routers
Set-Top Box, Cell phone
Handheld, Portable Equipment
72
IQ CPLDs for Industrial and Automotive
Applications
73
Introducing IQTM Products

• Why IQ?
• New range of devices with an extended Industrial
  Temperature option
• Consists of CPLD and FPGA families already
  available in
• I Grade - and the addition of selected
  devices with an extended temperature Q grade
  option
• IQ - its the intelligent choice for Automotive
  designers!!
• For FPGAs Q grade means
• -40C to 125C Junction Temperature
• For CPLDs Q Grade means
• -40C to 125C Ambient Temperature

Ambient the temperature of the air surrounding
the device Junction is the temperature of the
die in the package
74
Industrial and Automotive CPLDs
Density
512mc
2.5V

• Lowest power
• Highest speed
• Advanced features
• Additional security
• Smallest packages
• Lowest cost
• 3.3V tolerant
• 1.5V compatible
• Up to 4 I/O banks

• Low power
• 5V tolerant
• Small packaging

288mc

• Lowest cost 3.3V
• 5V tolerant
• Small packaging

• 3.3V tolerant
• Small packaging
• Up to 4 I/O banks

3.3V
1.8V
2.5V
Core Voltage
75
CPLD Software Improvements in 6.1

• Ease of use
• Improved CPLD process flow
• Single process (Implement Design) will pull the
  design through the entire fitting process
• Granular control still possible for power users
  by expanding individual processes
• New design creation aids
• New project wizard leads the user through the
  project creation process
• Add existing source / Create new source processes
  - assist in getting started faster
• Centralized process properties menu
• Web Update
• Built in utility checks for service packs and
  supplemental CPLD updates
• Downloads and installs update in single step

CPLD Software Update and Online Support
File Number Here
76
Xilinx Online Software Solutions

• Web-deliverable desktop and online design
  solutions for new, high volume markets
• Industrys broadest PLD product offering in a
  single downloadable solution
• Enables fastest time-to-market
• Easy to use design tools
• Easy to obtain via the web
• No license required
• Software upgrades available for online purchase

77
ISE 6.1i Software ImprovementsEase of Use

• Improved CPLD process flow
• Single process (Implement Design) will pull the
  design through the entire fitting process
• Detailed control still possible for power users
  by expanding individual processes
• New design creation aids
• New project wizard leads the user through the
  project creation process
• Add existing source / create new source processes
  - assist in getting started faster
• Centralized process properties menu

78
ISE 6.1i Software Improvements

• Web updates
• Built in utility checks for service packs and
  supplemental CPLD updates
• Downloads and installs update in single step

79
ISE 6.1i Software Improvements

• HTML report improvements
• Integrated browser in the project navigator
  environment
• Addition of the timing report to HTML format
• Improved graphical presentation and equation
  representation
• CPLD support in PACE
• Pin Assignment and Constraint Editor

80
Whats New in ISE 6.1i

• CoolRunner-II
• Supported in XPower
• Saturn support
• All devices in all ISE configurations
• Supported in XPower
• ISE WebPACK availability
• Web release on Sept 22
• Free CDs available from the Xilinx Online Store
• Shipping charges apply
• 3,400 downloads per month and growing!

81
Buy Products Online

• Links to the Xilinx eCommerce page

From WebFITTER
From WebPACK
82
Additional Web Based Information

• For additional CoolRunner-II product information
• http//www.xilinx.com/products/coolrunner2
• For other Xilinx CPLD related product information
• http//www.xilinx.com/products/cpldsolutions
• For CoolRunner-II resource CD
• http//www.xilinx.com/forms/coolrunner_literature

83
CPLD Software Improvements in 6.1

• Ease of use
• Improved CPLD process flow
• Single process (Implement Design) will pull the
  design through the entire fitting process
• Granular control still possible for power users
  by expanding individual processes
• New design creation aids
• New project wizard leads the user through the
  project creation process
• Add existing source / Create new source processes
  - assist in getting started faster
• Centralized process properties menu
• Web Update
• Built in utility checks for service packs and
  supplemental CPLD updates
• Downloads and installs update in single step

Customer Success Stories
File Number Here
84
CPLD Success StoriesCustomer 1
Design Win Factors

• Market Automotive
• Application Digital Audio Broadcast Car
  Radio
• Device XC9572XL-10TQ100I
• Competition Lattice
• Reasons Pin Locking
• Pricing
• Easy to use software

High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
85
CPLD Success StoriesCustomer 2
Design Win Factors
High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
Market Datacom Application Switching
Host Board
Processor Devices XC95144XL-10TQ100C
Competition ASIC Reasons High
performance Pin-locking Flexible
interface I/Os
86
CPLD Success StoriesCustomer 3
Design Win Factors
High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
Market Consumer Application MP3
Player Device XCR3032A-VQ44C
Competition None, no one could
meet low power Reasons Low power
Low Cost, small package Web-based
software
87
CPLD Success StoriesCustomer 4
Design Win Factors
Market Consumer Application
Fingerprint Point-of-Sale Terminal
Device XC95216 Competition
None Reasons On-the-fly changes
133 MHz performance Pin-locking
Superior technical support
High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
88
CPLD Success StoriesCustomer 5
Design Win Factors
Market Commercial Application
Hand-held Cable TV Tester Device
XC95288XL Competition
Quicklogic Reasons Design Flexibility Price
Performance
High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
89
CPLD Success StoriesCustomer 6
Market Telecom Application Voice
Synthesis Server Module
Device XCR3128 Competition
Lattice Reasons Power!
90
CPLD Success StoriesCustomer 7
Design Win Factors
Market Instrumentation Application
Microcontroller Emulator Device
XCR3128VQ100C Competition Altera Reasons
Power Performance ISP Capabilities
High Performance Time to Market Fit in
Existing Flow Package offering 5v 3.3v Low
cost Low power
91
LOW POWER 3.3V
LOW POWER 1.8V
3.3V
5V
2.5V
Remote Controls Digital Cameras PDAs Smart
Phones Test Equipment Web Pads Medical
Equipment Label Printers Mobile phone add-ons MP3
Players Web pads Payphones Smart Card
Readers Hand Held Games USB Applications Utility
Meters Data Logger
Portable PDAs Remote Controls Test
Equipment Medical Consumer Cell Phones MP3
Players Set Top Box Hand Held Games High
Speed Telecom Switches Routers
Motor Control Test Equipment Security
Systems Cable Modems Car Nav. Systems Cash
Registers Surveillance cameras Set Top
Boxes Access Controls Fax Machines Gaming
Machines Industrial Control
Tape Drives Power Supplies Modems Access
Controls Fax Machines Gaming Machines Industrial
Control DAB Car Radios TFT LCD Interface Radio
Comms Train Controller Slot Machine Digital
Printer
Telecomm Base Stations Encoders Decoders DECT
Phones Line Cards Industrial Control
XC9500

• 5v, 36-288 macrocells
• Low Cost
• 5ns / 200MHz
• Best Pin Locking
• JTAG
• High Endurance
• (10,000 program cycles)

• 1.8v, 32-512 macrocells
• Ultra Low Power
• Schmitt Trigger Inputs
• CoolCLOCK, DataGate
• 3.5ns / 303MHz
• Static power lt100uA
• I/Os - LVTTL, LVCMOS
• SSTL HSTL

• 2.5v, 36 - 288 macrocells
• Low Cost
• Best Pin Locking
• JTAG
• High Performance
• High Endurance
• 20 year data retention
• 4ns / 250 MHz

• 3.3v, 32-512 macrocells
• Low Power
• JTAG
• Logic Flexibility
• 5ns / 200MHz
• Static power lt100uA
• 20 year data retention
• 5V tolerant I/Os

• 3.3v, 36-288 macrocells
• Low Cost
• Best Pin Locking
• JTAG
• High Performance
• High Endurance
• 5ns / 200MHz

92
Xilinx CPLD Summary

• XC9500/XL/XV fast, higher voltage, low-cost
• For mainstream 5v, 3.3v 2.5v designs
• Great architectural features (ISP, JTAG,
  pin-locking)
• Coolrunner XPLA3 low power
• Pioneering low power 3.3v product with 5v
  tolerant I/O
• Lowest power 3.3v CPLD - 3x better than nearest
  3.3v competitor
• CoolRunner-II High Performance and Low Power
• Higher Performance High Speed (385MHz) at 1.8V
• Enhanced clocking I/O feature set
• Lowest power consumption
• DataGATE for even lower power operation
• Higher system reliability system security