Introduction to Xilinx PC

1
Introduction to Xilinx (PC)

• Michael Shyu
• gis86545_at_cis.nctu.edu.tw
• 2009/12/11

2
Outline

• Breadboard VS. FPLD with CAD
• Xilinx Design Flow
• Introduction to XC4000 Architecture
• Foundation and XACTstep Software
• An Example - Implementation of a Full Adder
• Supports

3
Breadboard
4
Field Programmable Logic Device

• Function is specified by the user after the
  device is manufactured.
• FPLD families
• SPLD (Simple Programmable Logic Device)
• CPLD (Complex Programmable Logic Device)
• XC9500
• FPGA (Field Programmable Gate Arrays)
• XC3000, XC4000, XC5200, XC6200

5
Flow of Digital Design
Generic Design Flow
Xilinx Design Flow
Get Specification
Define I/O
CAD
Design Entry
Function Simulation
Map, Place, Route
Timing Simulation
Download
Debug
6
FPLD with CAD is Better

• Build designs faster.
• Avoid mistakes caused by error in wiring.
• Save your designs.
• Experiment with many types of chips.
• Avoid or easily correct design error.
• Design larger projects.

7
(No Transcript)
8
(No Transcript)
9
(No Transcript)
10
(No Transcript)
11
(No Transcript)
12
(No Transcript)
13
(No Transcript)
14
(No Transcript)
15
Introduction to XC4000 Architecture
Intel Inside
16
(No Transcript)
17
(No Transcript)
18
(No Transcript)
19
(No Transcript)
20
(No Transcript)
21
(No Transcript)
22
(No Transcript)
23
(No Transcript)
24
(No Transcript)
25
(No Transcript)
26
(No Transcript)
27
(No Transcript)
28
(No Transcript)
29
(No Transcript)
30
(No Transcript)
31
Design a Full Adder
Input0
Sum
Full Adder
Input1
Carry Output
Carry Input
32
Schematic Design of a FA
33
Starting a New Project

• Start the Foundation Project Manager.
• File ? New Project
• Type the project name.
• Click OK.

34
Project Manager
35
Using the Schematic Editor

• Click on the Schematic Editor button.
• Complete the schematic.
• Options ? Create Netlist
• Options ? Export Netlist (in EDIF 200 format)
• Save the schematic and exit.

36
Simulate Function - Add Signals

• Click on the SIM Funct button.
• Signal ? Add Signals.
• Select the input and output signals you used.
• Click Add.
• Click Close.

37
Simulate Function - Add Simulators

• Signal ? Add Simulators.
• Select the Carry_Input and click the Bc2 in the
  Simulator Selection window.
• Repeat the above step to label B1, B0 on Input1,
  0.
• Click Close.

38
Simulate Function - the Results

• Click the Long button in the small, floating
  Simulator window.
• Check the output signals.
• Close the window and exit.

39
Assign the PIN Number

• Double-click the MY_FA.UCF in the Project Manager
  window to open it.
• Type the pin assignment description at the bottom
  of the file.
• Save and exit.

40
Compiling the Logic Design

• Click on the XACTstep M1 button to begin the
  compilation process.
• Design ? Implement
• Click the Options button.
• Enter the location of the pin assignment UCF into
  the USER Constraints.
• Click OK.

41
Compiling the Logic Design

• Click RUN.
• Hey! Congratulation, you have completed your
  design ( if theres no bug).
• Lets see whats inside.

42
EPIC Design Editor

• Tools ? EPIC Design Editor
• In the map of XC4005XL FPGA, you can see which
  block and routing resource are used.

43
Report Files

• How much of the XC4005XL FPGA was used to build
  the 1-bit adder?
• Did the compiler assign the inputs and outputs to
  the pins we requested?
• Find the answer in the report files.

44
PlaceRoute Report
45
Pad Report
46
Supports

• On Line Help
• Xilinx Book on CD
• Dyna Text Browser
• VLSI System Lab.
• http//vlsisun.cis.nctu.edu.tw
• ???? 708R
• Xilinx Supports
• CIC Supports

47
(No Transcript)
48
(No Transcript)