An Introduction to FPGA and SOPC Development Board

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An Introduction to FPGA and SOPC Development
Board

• Yong Wang

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Outline

• What are Programmable Logic Devices?
• Architecture and Examples
• Why FPGA?
• Vendors and Devices
• Development on Altera Device
• Summary

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Programmable Logic Devices

• Programmable digital integrated circuit
• Desired functionality is implemented by
  configuring on-chip logic blocks and
  interconnections
• Developers only care about the logic design but
  not the internal hard-wire connection (
  softwarelize the hardware design)

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ASIC vs. Programmable Logic Devices
ASIC (Application Specific Integrated Circuit) Programmable Chips
Longer design cycle and costlier ECO (Engineering Change order) Shorter design cycle and cheaper ECO
Faster performance Long delay
Lower cost if produced in high volume gt 10,000 chips Higher cost, good for medium to low volume products
Energy saving More power consumption
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Type of Programmable Logic Devices

• PLA (Programmable Logic Array)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field Programmable Gate Array)

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PLD - Sum of Products
Programmable AND array followed by fixed fan-in
OR gates
Programmable switch or fuse
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PLD - Macrocell

• Can implement combinational or sequential logic

Select
A
B
C
Enable
Flip-flop
MUX
D
Q
Clock
AND plane
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CPLD Structure

• Integration of several PLD blocks with a
  programmable interconnect on a single chip

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CPLD Example - Altera MAX7000
EPM7000 Series Block Diagram
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CPLD Example - Altera MAX7000
EPM7000 Series Device Macrocell
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FPGA - Generic Structure

• FPGA building blocks
• Programmable logic blocksImplement combinatorial
  and sequential logic
• Programmable interconnectWires to connect inputs
  and outputs to logic blocks
• Programmable I/O blocks Special logic blocks at
  the periphery of device for external connections

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Other FPGA Building Blocks

• Clock distribution
• Embedded memory blocks
• Special purpose blocks
• DSP blocks
• Hardware multipliers, adders and registers
• Embedded microprocessors/microcontrollers
• High-speed serial transceivers

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FPGA Basic Logic Element

• LUT to implement combinatorial logic
• Register for sequential circuits
• Additional logic (not shown)
• Carry logic for arithmetic functions
• Expansion logic for functions requiring more than
  4 inputs

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Look-Up Tables (LUT)

• Look-up table with N-inputs can be used to
  implement any combinatorial function of N inputs
• LUT is programmed with the truth-table

LUT implementation
Truth-table
Gate implementation
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LUT Implementation

• Example 3-input LUT
• Based on multiplexers (pass transistors)
• LUT entries stored in configuration memory cells

Configuration memory cells
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Other FPGA Building Blocks

• Clock distribution
• Embedded memory blocks
• Special purpose blocks
• DSP blocks
• Hardware multipliers, adders and registers
• Embedded microprocessors/microcontrollers
• High-speed serial transceivers

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Special Features

• Clock management
• PLL,DLL
• Eliminate clock skew between external clock input
  and on-chip clock
• Low-skew global clock distribution network
• Support for various interface standards
• High-speed serial I/Os
• Embedded processor cores
• DSP blocks

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Configuration Storage Elements

• Static Random Access Memory (SRAM)
• Logical configuration is controlled by the state
  of SRAM bits
• FPGA needs to be configured at power-on by
  another separated ROM
• Flash Erasable Programmable ROM (Flash)
• Logical configuration is implemented by
  floating-gate transistors that can be turned off
  by injecting charge onto its gate. FPGA itself
  holds the program
• reprogrammable, even in-circuit

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Example Altera Stratix Series
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Why FPGA?

• FPGA chips handle dense logic and memory elements
  offering very high logic capacity
• Uncommitted logic blocks are replicated in an
  FPGA with interconnects and I/O blocks
• Complete integrated design environment (IDE)
• Easy to learn and use
• Low cost of ownership

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FPGA Vendors

• Altera
• Xilinx
• Virtex-II/Virtex-4 Feature-packed
  high-performance SRAM-based FPGA
• Spartan 3 low-cost feature reduced version
• CoolRunner CPLDs
• Actel
• Lattice
• QuickLogic

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Introduction to Altera Devices

• Programmable Logic Families
• High Medium Density FPGAs
• Stratix II, Stratix, APEX II, APEX 20K, FLEX
  10K
• Low-Cost FPGAs
• Cyclone ACEX 1K
• FPGAs with Clock Data Recovery
• Stratix GX Mercury
• CPLDs
• MAX 7000 MAX 3000
• Embedded Processor Solutions
• Nios, ExcaliburT
• Configuration Devices
• EPC

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Nios The processor in software

• a user-configurable, 16-bit instruction set
  architecture (ISA), general-purpose RISC embedded
  processor
• designers can use the SOPC (system-on-aprogrammabl
  e-chip) Builder system development tool to very
  easily create custom processor-based systems

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What is available

• Altera Stratix Nios Development Board
• Altera UP2 Development Board

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Altera Stratix Nios Development Board
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Altera Stratix Nios Development Board

• Stratix EP1S10F780C6
• 10,570 Logic Elements
• 920 Kb on-chip memory
• Provide hardware platform for developing embedded
  system
• Comes pre-programmed with a 32-bit Nios processor
  reference design

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Altera Staratix Nios Development Board

• 8 MB of flash Memory,1MB of static RAM, 16MB of
  SDRAM
• On-board Ethernet MAC/PHY device
• Compact Flash connector hearder
• Two RS-232 DB9 serial ports
• 50MHz oscillator and zero-skew clock distribution
  circuitry
• Four push-button switches
• Dual 7-segment LED display

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Altera UP2 Development Board
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Altera UP2 Development Board

• EPF10K70RC240-4 device
• EPM7128SLC-7 device
• One RS-232 serial port
• Four push-button switches
• Dual 7-segment LED display
• 25.175MHz oscillator

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FPGA Design Flow
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FPGA Design Flow
Design Specification
Design Entry/RTL Coding Behavioral or Structural
Description of Design

• RTL Simulation
• Functional Simulation
• Verify Logic Model Data Flow
• (No Timing Delays)

LE

• Synthesis
• Translate Design into Device Specific Primitives
• Optimization to Meet Required Area Performance
  Constraints

MEM
I/O

• Place Route
• Map Primitives to Specific Locations inside
• Target Technology with Reference to Area
• Performance Constraints
• Specify Routing Resources to Be Used

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FPGA Design Flow
Timing Analysis - Verify Performance
Specifications Were Met - Static Timing Analysis
tclk
Gate Level Simulation - Timing Simulation -
Verify Design Will Work in Target Technology
Program Test - Program Test Device on Board
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Design Entry Methods

• Text-based
• VHDL(Very High Speed Integrated Circuit Hardware
  Description Language)
• Verilog HDL

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Block Diagram

• Contents of a block can be any type of design unit

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State Diagram

• Bubble diagram
• States
• Conditions
• Transitions
• Outputs
• Useful for developing control modules

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Program Devices

• Once we verify our design, it should be
  downloaded to the FPGA devices
• Designs can be downloaded through parallel port
  in PC to the JTAG connector on board using
  download cables
• Designs can also be downloaded via the Internet
  to a target device

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Introduction to Altera Design Software

• Software Development Tools
• Quartus II
• Stratix II, Stratix, Stratix GX, Cyclone, APEX
  II, APEX 20K/E/C, Excalibur, Mercury Devices
• FLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX
  7000S/AE/B, MAX 3000A Devices
• Quartus II Web Edition
• Free Version
• Not All Features Devices Included
• MAXPLUS II
• All FLEX, ACEX, MAX Devices

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Quartus II Development System

• Fully-Integrated Design Tool
• Multiple Design Entry Methods
• Logic Synthesis
• Place Route
• Simulation
• Timing Power Analysis
• Device Programming

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More Features

• MegaWizard SOPC Builder Design Tools
• LogicLock Optimization Tool
• NativeLink 3rd-Party EDA Tool Integration
• Integrated Embedded Software Development
• SignalTap II SignalProbe Debug Tools
• Windows, Solaris, HPUX, Linux Support
• Node-Locked Network Licensing Options
• Revision Control Interface

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Quartus II Operating Environment
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Main Toolbar Modes
Dynamic menus
Compiler Report
Floorplans
Execution Controls
Window new file buttons
To Reset Views Tools ?ToolbarsgtReset
All Restart Quartus II
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Previous Project 1 VGA Driver

• 25Mhz clock (640 480)
• Horizontal, Vertical Sync
• RGB

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Previous Project 2 DRIIVE Network
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Summary

• Prerequisite
• Electronics and circuits
• Digital logic design
• VHDL (VHSIC Hardware Description Language)
• FPGA
• Combine technologies in hardware software
• Benefits