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FPGA devices

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Spartan-3 Family General Architecture. George Mason University ... Spartan-3 Block RAM Amounts. 29. ECE 448 FPGA and ASIC Design with VHDL ... – PowerPoint PPT presentation

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Title: FPGA devices


1
FPGA devices
ECE 448 Lecture 6
2
Required reading (1)
  • S. Brown and Z. Vranesic, Fundamentals of
    Digital Logic with VHDL Design
  • Chapter 3.6.5 Field-Programmable Gate Arrays

3
Required Reading (2)
  • Xilinx, Inc.
  • Spartan-3 FPGA Introduction
  • Features
  • Architectural Overview
  • Package Marking
  • Spartan-3 FPGA Functional Description
  • CLB Overview,
  • Block RAM Overview
  • Dedicated Multipliers
  • Interconnect

4
World of Integrated Circuits
Integrated Circuits
Full-Custom ASICs
Semi-Custom ASICs
User Programmable
SPLD
FPGA
CPLD
PAL
PLA
PML
LUT (Look-Up Table)
MUX
Gates
5
Two competing implementation approaches
FPGA Field Programmable Gate Array
ASIC Application Specific Integrated Circuit
  • designed all the way
  • from behavioral description
  • to physical layout
  • no physical layout design
  • design ends with
  • a bitstream used
  • to configure a device
  • designs must be sent
  • for expensive and time
  • consuming fabrication
  • in semiconductor foundry
  • bought off the shelf
  • and reconfigured by
  • designers themselves

6
What is an FPGA?
Configurable Logic Blocks
I/O Blocks
Block RAMs
7
Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in high volumes
Reconfigurability
8
Other FPGA Advantages
  • Manufacturing cycle for ASIC is very costly,
    lengthy and engages lots of manpower
  • Mistakes not detected at design time have large
    impact on development time and cost
  • FPGAs are perfect for rapid prototyping of
    digital circuits
  • Easy upgrades like in case of software
  • Unique applications
  • reconfigurable computing

9
Major FPGA Vendors
  • SRAM-based FPGAs
  • Xilinx, Inc.
  • Altera Corp.
  • Atmel
  • Lattice Semiconductor
  • Flash antifuse FPGAs
  • Actel Corp.
  • Quick Logic Corp.

Share over 60 of the market
10
Xilinx
  • Primary products FPGAs and the associated CAD
    software
  • Main headquarters in San Jose, CA
  • Fabless Semiconductor and Software Company
  • UMC (Taiwan) Xilinx acquired an equity stake in
    UMC in 1996
  • Seiko Epson (Japan)
  • TSMC (Taiwan)

ISE Alliance and Foundation Series Design
Software
11
Xilinx FPGA Families
  • Old families
  • XC3000, XC4000, XC5200
  • Old 0.5µm, 0.35µm and 0.25µm technology. Not
    recommended for modern designs.
  • High-performance families
  • Virtex (0.22µm)
  • Virtex-E, Virtex-EM (0.18µm)
  • Virtex-II, Virtex-II PRO (0.13µm)
  • Virtex-4 (0.09µm)
  • Low Cost Family
  • Spartan/XL derived from XC4000
  • Spartan-II derived from Virtex
  • Spartan-IIE derived from Virtex-E
  • Spartan-3

12
(No Transcript)
13
Spartan-3 Family General Architecture
14
CLB Structure
15
CLB Structure
16
CLB Slice Structure
  • Each slice contains two sets of the following
  • Four-input LUT
  • Any 4-input logic function,
  • or 16-bit x 1 sync RAM (SLICEM only)
  • or 16-bit shift register (SLICEM only)
  • Carry Control
  • Fast arithmetic logic
  • Multiplier logic
  • Multiplexer logic
  • Storage element
  • Latch or flip-flop
  • Set and reset
  • True or inverted inputs
  • Sync. or async. control

17
LUT (Look-Up Table) Functionality
  • Look-Up tables are primary elements for logic
    implementation
  • Each LUT can implement any function of 4 inputs

18
5-Input Functions implemented using two LUTs
  • One CLB Slice can implement any function of 5
    inputs
  • Logic function is partitioned between two LUTs
  • F5 multiplexer selects LUT

19
5-Input Functions implemented using two LUTs
OUT
20
Distributed RAM
  • CLB LUT configurable as Distributed RAM
  • A LUT equals 16x1 RAM
  • Implements Single and Dual-Ports
  • Cascade LUTs to increase RAM size
  • Synchronous write
  • Synchronous/Asynchronous read
  • Accompanying flip-flops used for synchronous read

21
Shift Register
  • Each LUT can be configured as shift register
  • Serial in, serial out
  • Dynamically addressable delay up to 16 cycles
  • For programmable pipeline
  • Cascade for greater cycle delays
  • Use CLB flip-flops to add depth

22
Shift Register
  • Register-rich FPGA
  • Allows for addition of pipeline stages to
    increase throughput
  • Data paths must be balanced to keep desired
    functionality

23
Carry Control Logic
COUT
YB
Look-Up Table
Carry Control Logic
Y
G4 G3 G2 G1
S
D
Q
O
CK
EC
R
F5IN
BY SR
XB
Look-Up Table
Carry Control Logic
X
S
F4 F3 F2 F1
D
Q
O
CK
EC
R
CIN CLK CE
SLICE
24
Fast Carry Logic
  • Each CLB contains separate logic and routing for
    the fast generation of sum carry signals
  • Increases efficiency and performance of adders,
    subtractors, accumulators, comparators, and
    counters
  • Carry logic is independent of normal logic and
    routing resources

MSB
Carry Logic Routing
LSB
25
Accessing Carry Logic
  • All major synthesis tools can infer carry logic
    for arithmetic functions
  • Addition (SUM lt A B)
  • Subtraction (DIFF lt A - B)
  • Comparators (if A lt B then)
  • Counters (count lt count 1)

26
Block RAM(BRAM)
27
Block RAM
  • Most efficient memory implementation
  • Dedicated blocks of memory
  • Ideal for most memory requirements
  • 4 to 104 memory blocks
  • 18 kbits 18,432 bits per block (16 k without
    parity bits)
  • Use multiple blocks for larger memories
  • Builds both single and true dual-port RAMs

28
Spartan-3 Block RAM Amounts
29
Positions of Block RAM Columns
30
Block RAM Port Aspect Ratios
1
2
4
0
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
81
0
2k x (81)
2047
162
0
1024 x (162)
1023
16,383
31
Block RAM Port Aspect Ratios
32
Single-Port Block RAM
33
Dual-Port Block RAM
34
Dual-Port Bus Flexibility
RAMB4_S16_S8
WEA
Port A Out 18-Bit Width
Port A In 1K-Bit Depth
ENA
RSTA
DOA170
CLKA
ADDRA90
DIA170
WEB
Port B Out 9-Bit Width
Port B In 2k-Bit Depth
ENB
RSTB
DOB80
CLKB
ADDRB100
DIB80
  • Each port can be configured with a different data
    bus width
  • Provides easy data width conversion without any
    additional logic

35
Two Independent Single-Port RAMs
RAMB4_S1_S1
Port A In 8K-Bit Depth
Port A Out 1-Bit Width
0, ADDR120
Port B In 8K-Bit Depth
Port B Out 1-Bit Width
1, ADDR120
  • To access the lower RAM
  • Tie the MSB address bit to Logic Low
  • To access the upper RAM
  • Tie the MSB address bit to Logic High
  • Added advantage of True Dual-Port
  • No wasted RAM Bits
  • Can split a Dual-Port 16K RAM into two
    Single-Port 8K RAM
  • Simultaneous independent access to each RAM

36
Block RAM Waveforms WRITE_FIRST
37
Block RAM Waveforms READ_FIRST
38
Block RAM Waveforms NO_CHANGE
39
Embedded Multipliers
40
18 x 18 Embedded Multiplier
  • Fast arithmetic functions
  • Optimized to implement
  • multiply / accumulate modules

41
18 x 18 Multiplier
  • Embedded 18-bit x 18-bit multiplier
  • 2s complement signed operation
  • Multipliers are organized in columns

42
Positions of Multipliers
43
Asynchronous 18-bit Multiplier
44
18-bit Multiplier with Register
45
Input/Output Blocks(IOBs)
46
Basic I/O Block Structure
D
Q
Three-State
EC
FF Enable
Three-StateControl
Clock
SR
Set/Reset
D
Q
Output
EC
FF Enable
Output Path
SR
Direct Input
FF Enable
Input Path
D
Q
Registered Input
EC
SR
47
IOB Functionality
  • IOB provides interface between the package pins
    and CLBs
  • Each IOB can work as uni- or bi-directional I/O
  • Outputs can be forced into High Impedance
  • Inputs and outputs can be registered
  • advised for high-performance I/O
  • Inputs can be delayed

48
Routing Resources
49
Routing Resources
50
Long and Hex Lines
51
Double and Direct Lines
52
Spartan-3 Family Attributes
53
Spartan-3 FPGA Family Members
54
FPGA Nomenclature
55
Device Part Marking
Were Using XC3S100-4FG256
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