COOLRUNNER II REAL DIGITAL CPLD

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COOLRUNNER IIREAL DIGITAL CPLD

• Ravi Kumar Vommina
• CPE 695

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Contents

• Introduction
• Features
• Architecture
• Advanced Features
• Applications
• ISE 6.1
• Cool Runner II Family parameters

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Introduction

• Reconfigurable Computing Platforms
• Implementing algorithms directly in hardware
• Parallelism nature of Hardware
• Efficient Implementation
• FPGA (Field Programmable gate Array)
• Configurable logic blocks and routing resources
• CLB uses LUTs to implement Boolean functions
• Inclusion of hard cores
• CPLD (Complex programmable logic device)
• PLA , programmable AND plane,fixed OR plane
• PAL, both AND and OR planes

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Introduction
PAL Requires 4 pts!
PLA Requires only 3 pts!
C
B
A
C
B
A
X A B C Y A B !C
Can NOT share common logic
Y
X
X
Y
Indicates used junction
Common logic may be shared in Cool Runner II
Indicates unused junction
Indicates fixed junction
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Cool Runner II Features

• Real Digital
• patented design technology enabling high
  performance and ultra low power consumption.
• true CMOS both in process technology and design
  technique
• 1.8 V system, fastest low power CPLD using real
  digital technology
• 0.18u process technology CMOS CPLD
• Static Icc of less than 100 micro amps at all
  times
• 100 CMOS product term generation

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CMOS
V
DD

• In steady state there exist always a finite
  resistance path between Vout and either VDD or
  Ground.
• Ideal static power should be zero
• Small static power consumption exists due to
  leakage currents and sub threshold conduction
  that is lt 100 micro amps
• Total power dynamicshort circuit static
• Short circuit current flow is due to the delay in
  rise and fall times of input.
• Dynamic power C .VDD2/ 2 . f

CMOS inverter
V
V
in
out
C
L
V
V
DD
DD
R
p
V
out
V
out
R
n
V
V
V
0
5
5
in
DD
in
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Product term generation
Distributed RC model (Elmore
delay) tpHL 0.69 Reqn(C12C23C34CL) Design
for speed Alternative structures
A
B
C
D
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100 CMOS Product Generation
Delay lt 0.1ns
Delay lt 0.3ns
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Cool Runner Architecture High Level View
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Cool Runner II Macro cell view
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Global Clock Signals

• Clock input is buffered that drives multiple
  internal global signal traces to deliver low skew
  and reduce loading delays

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Recap

• High level View
• 16 macro cells in a function block
• Function blocks use PLA
• Function blocks interconnect with advanced
  interconnect matrix
• AIM is highly connected low power rapid switch
• Macro cell View
• 56 product terms
• 4 control terms, 3 product terms
• One flipflop as (D,T or latch) , ( edge or dual
  edge triggered)
• Xilinx software makes the choice when to choose
  product or global or control term

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Cool Runner-II I/O Characteristics
Programmable Output capabilities

• performed with software attributes
• Open drain with pull up
• Slew rate

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Cool Runner II input view
Schmitt Trigger Input
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Cool Runner II Input Characteristics

• Termination Options
• Bus- Hold (Weak Keeper)
• Pull-Up
• CGND
• During power up device is in Quiescent state

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Advanced Features Data Gate
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Advanced Features Clocking Options
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Advanced Features-Cool Clock
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Using the advanced features

• Clock divide
• declaration
• Instantiation
• Schmitt Trigger input

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Advanced Features-On the fly Configuration

• Initial pattern is loaded into a configuration
  shifter
• The pattern first transfers into nonvolatile
  memory
• The pattern is then read from NV to SRAM for
  actual cell operation
• Leaves ability to reload the NV memory as xilinx
  says, On the Fly

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Impact Menu
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Selecting OTF
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Cool Runner II Features

• Advanced Design Security
• Hot Pluggable
• Wide package availability
• Supports Multi Voltage standards

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Applications

• Ideal for high speed designs
• High performance CPLD
• Advanced features
• Double data rates
• Target device for portable designs
• Lowest power
• Maximum battery life
• Lower heat dissipation
• Small packaging
• Chip scale packaging

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PDA
IrDA
LED
?P
UART
Docking Cradle
LCD
SPI
Touchscreen
Keypad
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Interface for DDR SDRAM Interface

• Double data rates
• Address translation

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ISE6.1Design Flow

• An active project space is created.
• Existing VHDL modules can be added or new ones
  can be created in the project.
• A user constraint file is specified that maps the
  input and out put signals to the actual pins of
  the device
• Synthesis of the design is performed by just
  selecting the implement design option.
• Device is configured by IMPACT.

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Cool Runner II
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Bibliography

• WWW.Xilinx.com
• http//bwrc.eecs.berkeley.edu/IcBook/