Ch.4 RTL Design

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Ch.4 RTL Design

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Standard Cell Design Ch.4 RTL Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology – PowerPoint PPT presentation

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Title: Ch.4 RTL Design

1
Ch.4 RTL Design
Standard Cell Design
TAIST ICTES Program VLSI Design
Methodology Hiroaki Kunieda Tokyo Institute of
Technology
2

4.1 Basic Components

3
Logic Design
RTL Simulation
RTL
Logic Synthesis
Functional Verification
Scan Netlist
Scan Path Design
Functional Verification
Synthesis Netlist
Timing Analysis
4
VerilogHDL I
This level describes a system by concurrent
algorithms (Behavioral). Each algorithm itself is
sequential, that means it consists of a set of
instructions that are executed one after the
other. Functions, Tasks and Always blocks are the
main elements. There is no regard to the
structural realization of the design.
Behavior Level
Designs using the Register-Transfer Level specify
the characteristics of a circuit by operations
and the transfer of data between the registers.
An explicit clock is used. RTL design contains
exact timing bounds operations are scheduled to
occur at certain times. Modern RTL code
definition is "Any code that is synthesizable is
called RTL code".
RTL Level (Structural Level)
Within the logic level the characteristics of a
system are described by logical links and their
timing properties. All signals are discrete
signals. They can only have definite logical
values (0', 1', X', Z). The usable
operations are predefined logic primitives (AND,
OR, NOT etc gates). Using gate level modeling
might not be a good idea for any level of logic
design. Gate level code is generated by tools
like synthesis tools and this netlist is used for
gate level simulation and for backend.
Gate Level
5
VerilogHDL II

reg memory elements. Substitute in always
sentence.(lt, )
wire signal wire in modules. Substitute in
assign sentence.
Blocking substitution, affected by right
variable, sequentially.
a b
c a // c is equivalent to b value
lt Non Blocking, changed by clock timing in
parallel.
a lt b
c lt a //c and a behaves as shift register.
Signal level x, o, 1, z
Strength of signal supply, strong, pull, large,
weak, medium, small, highz
parameter to decide the bit size.
assign 10 x a b //assign after 10 nsec

6
VerilogHDL III
Behavior Description with Procedure Block
initial once always repetitive
reg out wire a, b, sel always _at_( a or b or sel
) if(sel 1b1) out a else if ( sel
1b0 ) out b else out 1bx Note reg
is used in procedure block for left
term.

initial
begin
a 1b0 // a0 at t0
10 a 1b1 // a1 at t10
20 a 1b0 // a0 at t20
end

7
VerilogHDL IV

Blocking
always _at_(posedge clock) // q and qr is replaced
begin
qd
qrd
end
Non Blocking //exchange a and b by positive edge
of clock
always _at_(posedge clock)
begin
altb
blta
end // ab ba makes both a and b
to be old b value.

8
VerilogHDL V
function 7 0 sign_extend input 3 0
a if ( a 3 ) sign_extend 4b1111,
a else sign_extend 4b0000, a
endfunction x lt sign_extend( a )
task sign_extend input 3 0 a output
7 0 x if ( a 3 ) x 4b1111, a
else x 4b0000, a endtask sign_extend( a,
x )
Tasks are used in all programming languages,
generally known as procedures or subroutines. The
lines of code are enclosed in task....end task
brackets. Data is passed to the task, the
processing done, and the result returned. They
have to be specifically called, with data ins and
outs, rather than just wired in to the general
netlist. Included in the main body of code, they
can be called many times, reducing code
repetition.
A Verilog HDL function is the same as a task,
with very little differences, like function
cannot drive more than one output, can not
contain delays.
Concatenation 8bit data of sign_extend is made
by combining 2 4bits-data
9
EXOR Gates with Delay

module hard_eor(c, a, b)
output c
input a, b
wire d, e, f
nand 4 g1(d, a, b)
nand 4 g2(e, a, d)
nand 4 g3(f, b, d)
nand 8 g4(c, e, f)
endmodule

10
Mutiplexer

module mux(f, a, b, sel)
output f
input a, b, sel
wire not_sel
and g1(f1, a, not_sel), g2(f2, b, sel)
or g3(f, f1, f2)
not g4(not_sel, sel)
endmodule

11
Decoder

module decoder(data_in, data_out)
input10 data_in
output30 data_out
always _at_(data_in)
begin
case(data_in)
2b00data_outlt4b0001
2b01data_outlt4b0010
2b10data_outlt4b0100
2b11data_outlt4b1000
default data_outlt4bxxxx // the case not
described
endcase
end
endmodule

12
Priority Encoder

module encoder(data_in, data_out)
input30 data_in
output10 data_out
always _at_(data_in)
begin
case(data_in)
4b0001data_outlt2b00
4b001xdata_outlt2b01
4b01xxdata_outlt2b10
4b1xxxdata_outlt2b11
default data_outlt2bxx // the case not
described
endcase
end
endmodule

13
Adder (structure description)

module adder(sum, a, b)
output sum
input a, b
wire10 a, b
wire20 sum
wire c
half_adder hal(c, sum0, a0, b0)
full_adder fal(sum2, sum1, a1, b1, c)
endmodule

14
Adder (behavior description)

module adder(sum, a, b)
parameter size12, delay8
inputsize-10 a, b
outputsize-10 sum
always _at_(a or b)
delay sab
endmodule

15
ALU (Arithmetic and Logic Unit)

module alu(out, in_a, in_b, cntrl)
parameter size8
input in_a, in_b, ctrl
output out
wire size-10 in_a, in_b, out
wire 50 cntrl
always _at_(cntrl)
begin
case(cntrl)
6b000010outltin_a
6b000110outlt(in_ain_b)
6b001010outlt(in_a)in_b
6b001110outlt0
6b010010outlt(in_a in_b)
6b010110outltin_b

6b101110outlt in_a in_b
6b110010outlt1 6b110110outlt in_a
(in_b) 6b111010outlt in_a in_b
6b111110outlt in_a defaultoutltx
endcase end endmodule
16
Register

module register(data_out, data_in, load, resetn,
clk)
parameter size16
input data_in, resetn, clk
output data_out
wire size-10 data_in
reg size-10 data_out
wire resetn, load, clk
always _at_(posedge clk or negedge resetn)
begin
if(resetn)
data_out0
else
if(load)
data_outdata_in
end
endmodule

17
Counter_Register

module counter_register(data_out, data_in, load,
inc, resetn, clk)
parameter size16
input data_in, reset, inc, clk
output data_out
wire size-10 data_in
reg size-10 data_out
wire resetn, load, clk
always _at_(posedge clk or negedge resetn)
begin
if(resetn)
data_out0
else
if(load)
data_outdata_in
else
begin
if(inc)
data_outdata_out1
end

18
Tristate Buffer (Bus driver)

module tristate_buffer(data_out, data_in,
enable)
parameter size16
input data_in, enable
output data_out
inputsize-10 data_in
outputsize-10 data_out
wire enable
always _at_(data_in or enable)
begin
if(enable 1)
data_outdata_in
else if(enable0)
data_outbz
else
data_outbx
end
endmodule

19
State Machine
parameter s02b00, s12b01, s22b11,
s32b10 always _at_(posedge clock) current_state
ltnext_state always _at_(current_state or input)
begin case(current_state) s0
next_statelt(input0)?s1s0 s1
next_statelt(input1)?s2s0 s2
next_statelts3 s3 next_statelts0
defaultnext_statelts0 endcase end
always _at_(current_state or input)
begin case(current_state) s0
outputlt0 s1 outputlt0 s2
outputlt0 s3 outputlt1
defaultoutputlt0 endcase end
20

4.2 Processor Example

21
Data Path 1
22
Data Path 1
module datapath 1 (InputA, OutputB, loadA, loadB,
clk) input InputA, loadA, loadB, clk
Output OutputB wire 70 InputA, OutputB
wire load_A, load_B, clk reg 70
OutputA, OutputB always _at_(posedge clk)
begin if(loadA 1) OutputA lt
InputA if(loadB 1) OutputB lt OutputA
end endmodule
23
module controller(start, Input, loadA, loadB,
clk) parameter S03b000, S13b010,
S23b100 begin always _at_(posedge clock)
current_stateltnext_state always
_at_(current_state or input) begin
case(current_state) S0 next_statelt
(Input)?S1S0 S1 next_statelt S0 S2
next_statelt S1 defaultnext_statelts0
endcase end always
_at_(current_state or input) begin
HOLD_REQ0 ADR_ENn1 ADR_STB0 DMA_ACK0
IOR_OUTn1 Dbout_STB0//default
case(current_state) s1 loadA lt1
S2 loadB lt1 endcase
endendmodule
Controller (State Machine)
24
Architecture of Micro Processor
25
Computer System

module CPU(resetn, clk)
input resetn, clk
wire 120 A_bus
wire 150 D_bus
wire 70 cntrl1, cntrl2, cntrl3
wire CEn, WEn, OEn
data_path dp1(A_bus, D_bus, cntrl1, cntrl2,
cntrl3, resetn, clk)
memory sram1(A_bus, CEn, WEn, OEn D_bus)
controller cntl1(cntrl1, cntrl2, cntrl3,
resetn, clk)
endmodule

26
Data Path I

module data_path(A_bus, D_bus, cntrl1, cntrl2,
cntrl3, resetn, clk)
input cntrl1, cntrl2, cntrl3, resetn, clk
inout A_bus, D_bus
wire 120 A_bus
wire 150 D_bus
wire 70 cntrl1, cntrl2, cntrl3
wire reestn, clk
reg 150 AC_out, IR_out
reg 110 PC_out
reg 70 INPR_out, OUTR_out
wire 150 ALU_out, IR_in
wire 110 PC_in
wire 70 INPR_in, OUTR_in

27
Data Path II
always // Control Circuits begin
AC_inALU_out ld_PC tbuff_PC
inc_PC ld_IR tbuff_IR op_ALU
ld_AC tbuff_AC tbuff_INPR
ld_OUTR Cen Oen WEn- end
28
Data Path III

RAM32 ram1(ABUS, CEn, WEn, OEn, DBUS)
alu alu1(ALU_out, AC_out, D_bus, c_ALU)
register 16 AC1(AC_out, AC_in,
ld_AC, resetn, clk)
tristate_buffer 16 AC_buffer1(D_bus,
AC_out, tbuff_AC)
couter_register 12 PC1(PC_out, PC_in, ld_PC,
inc_PC, resetn, clk)
tristate_buffer 12 PC2(D_bus, PC_out,
tbuff_PCDBUS)
tristate_buffer 12 PC2(A_bus, PC_out,
tbuff_PCABUS)
register 16 IR1(IR_out, D_bus, ld_IR,
resetn, clk)
tristate_buffer 16 IR_buffer1(D_bus,
IR_out, tbuff_IRDBUS)
tristate_buffer 12 IR_buffer2(A_bus,
IR_out110, tbuff_IRABUS)
register 8 INPR(INPR_out, INPR_in,
ld_INPR, resetn, clk)
tristate_buffer 8 INPR_buffer(D_bus,
INPR_out, tbuff_INPR)
register 8 OUTR(OUTR_out, D_bus,
ld_OUTR, resetn, clk)
tristate_buffer 8 OUTR_buffer(D_bus,
OUTR_out, tbuff_OUTR)
endmodule

29
Register

module register(data_out, data_in, load, resetn,
clk)
parameter size16
input data_in, resetn, clk
output data_out
wire size-10 data_in
reg size-10 data_out
wire resetn, load, clk
always _at_(posedge clk or negedge resetn)
begin
if(resetn)
data_out0
else
if(load)
data_outdata_in
end
endmodule

30
Counter_Register

module counter_register(data_out, data_in, load,
inc, resetn, clk)
parameter size16
input data_in, reset, inc, clk
output data_out
wire size-10 data_in
reg size-10 data_out
wire resetn, load, clk
always _at_(posedge clk or negedge resetn)
begin
if(resetn)
data_out0
else
if(load)
data_outdata_in
else
begin
if(inc)
data_outdata_in1
end

31
Tristate Buffer (Bus driver)

module tristate_buffer(data_out, data_in,
enable)
parameter size16
input data_in, enable
output data_out
inputsize-10 data_in
outputsize-10 data_out
wire enable
always _at_(data_in or enable)
begin
if(enable 1)
data_outdata_in
else if(enable0)
data_outbz
else
data_outbx
end
endmodule

32
ALU

module alu(out, a, b, c_alu)
parameter size8
input a, b, c_alu
output out
wire size-10 a, b, out
wire 20 c_alu
always _at_(c_alu)
begin
case(c_alu)
3b000 outlt a // trasfer
3'b001 outlt a1 // increment
3'b010 outlt a b // add
3'b011 outlt a(b)1 // subtract
3'b100 outlt b // load
3'b101 outlt a and b // and
3'b110 outlt a(b)1 // subtract
3'b111 outlt (a) // complement
defaultoutlt x
endcase

4.3 Memory

34
SRAM read cycle
CEnOEn0
35
SRAM write cycle
WEn Controlled
CEn Controlled
36
Asynchronous SRAM I

module RAM32 (A, CEn, WEn, OEn, DQ)
input 252 Adr // External memory
address
inout 310 DQ // External memory data
I/O
input CEn // Chip enable
input WEn // Write enable
input OEn // Output enable
define RAMDEPTH 1024 // Memory depth in Kbytes
reg 310 Ram 0((RAMDEPTH 1024) - 1)
// Memory register array
reg PosedgeWEn
// Rising edge of write enable
reg 150 Adr_Latch
// Latched address during writes
reg 70 TRI_DQ
// Tri-state data out

37
Asynchronous SRAM II
always _at_(posedge WEn) // Detects the rising edge
of WEn begin PosedgeWEn 1'b1 5
PosedgeWEn 1'b0 end // Read Cycle
CEnOEn1 always _at_(CEn or WEn or OEn or Adr or
PosedgeWEn) begin if (CEn OEn WEn)
TRI_DQ RamAdr else if (CEn
WEn) begin Adr_Latch Adr
// Latch address at start of write
TRI_DQ 8'hzz end
38
Asynchronous SRAM II
else if (PosedgeWEn) begin
RamAdr_Latch DQ
PosedgeWEn 1 1'b0 // Delay added so that
shows up on waveform view end else
TRI_DQ 8'hzz end assign 2 DQ
TRI_DQ Endmodule
39

4.4 State Machine

40
Control Circuit (State Machine Type)
Decoder
S Z FGI FGO
Combinational Logic
CF170
Control words
CF270
CF370
41
module controller( parameter T04b0000,
T14b0001, T24b0010, T34b0011,
T44b0100, T54b0101, T64b0110,
T74b0111 always _at_(posedge clock) current_sta
teltnext_state always _at_(current_state or
input) begin case(current_state) T0
next_statelt (S)?T1T0 T1 next_statelt
T2 T2 next_statelt T3 T3
next_statelt (T)?T4T0 T4 next_statelt
(T)?T5T0 T5 next_statelt (T)?T6T0
T6 next_statelt (T)?T7T0 T7 next_state
lt T0 defaultnext_statelts0 endcase
end
Controller (State Machine)
42
State Machine III (output)
CF11ltT3 and AI2
CF12ltT5 and MI1
CF13lt(T5 and MI2) or (T5 and MI6 )
CF14ltT5 and MI3
CF15ltT5 and MI3
CF16ltT3 and AI1
CF17ltT3 and AI0
43
State Machine IV (output)
CF21lt(T3 and MIALL) or T2
CF22lt(T4 and MI0) or ( T4 and MI0) or (T4 and MI2) or (T4and MI3) or (T4 and MI4) or ( T4 and MI6)
CF23ltT1
CF24ltT3 and IO5
CF25ltT5a and MI5
CF31lt(T3 and ( FGI) and IO2) or (T3 and (FGO) and IO3) or (S and T3 and AI3) or (Z and T3 and AI4) or (T6 and Z and MI6) or T1
CF32ltT4 and MI5
CF34ltT3 and IO0
CF35ltT3 and IO1
CF36ltT0
CF37ltT3 and IO4
44
State Machine III (output)
Tlt((M1 or M2 or M3 or M4 or M5) and T5) or (M6 and T6) or (AIALL and T3) or (IOALL and T3)
end endmodule
45

4.5 DMA Controller

46
DMA
Memory
Micro Processor
I/O Unit
DMA Controller
DMA stands for Direct Memory Access. I/.O Unit
accesses memory Directly while micro processor is
idle.
47
DMA memory to I/O
CLOCK
DMA_REQ (Input)
HOLD_REQ
HOLD_ACK(Input)
ADR_EN
ADR_STB
Dbout70
DMA_ACK
IOR_OUTn
EOP_Inn (Input) (end of operation)
48
State Diagram
49
State Diagaram
Current_ state Hold- REQ ADR_ EN ADR_ STB DMA_ ACK IOR_ OUTn Dbout_ STB
S0 1
S1 1 1
S2 1 1 1 1
S3 1 1 1 1 1
S4 1 1 1 1
S5 1 1 1 1
DMA_REQ HOLD_ ACK EOP_Inn Current_state Next_ state
0 S0 S0
1 S0 S1
0 S1 S1
1 S1 S2
S2 S3
S3 S4
S4 S5
1 S5 S3
0 S5 S0
50
parameter s03b000, s13b001, s23b010,
s32b011, s43b100, s53b101 always
_at_(posedge clock) current_stateltnext_state alw
ays _at_(current_state or input)
begin case(current_state) s0
next_statelt(DMA_REQ)?s1s0 s1
next_statelt(HOLD_ACK)?s2s1 s2
next_statelts3 s3 next_statelts4 s4
next_statelts5 s5 next_statelt(EOP_Inn)?s0
s3 defaultnext_statelts0 endcase end
State Machine I
51
State Machine II