RTL%20Systems

1
RTL Systems

• References
• Introduction to Digital System by Milos
  Ercegovac,Tomas Lang, Jaime H. Moreno wiley
  publisher
• Digital Design Principles Practices by
  J.F.Wakerly, Pearson Education Press, 2007

2
Introduction

• 1. DATA SUBSYSTEM (datapath) AND CONTROL
  SUBSYSTEM
• 2. THE STATE OF DATA SUBSYSTEM
• CONTENTS OF A SET OF REGISTERS
• 3. THE FUNCTION OF THE SYSTEM PERFORMED AS A
  SEQUENCE OF REGISTER TRANSFERS (in one or more
  clock cycles)?
• 4. A REGISTER TRANSFER
• A TRANSFORMATION PERFORMED ON A DATA

3
Introduction(cont..)?

• THE SEQUENCE OF REGISTER TRANSFERS CONTROLLED BY
  THE CONTROL SUBSYSTEM (a sequential system)?
• TRANSFERRED FROM ONE REGISTER TO ANOTHER

4
Organization of Systems

• TWO FUNCTIONS
• DATA TRANSFORMATIONS FUNCTIONAL UNITS
  (operators)?
• - CONTROL OF DATA TRANSFORMATIONS AND THEIR
  SEQUENCING CONTROL UNITS
• TYPES OF SYSTEMS WITH RESPECT TO FUNCTIONAL
  UNITS
• NONSHARING SYSTEM
• SHARING SYSTEM
• UNIMODULE SYSTEM

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CENTRALIZED CONTROL
6
DeCENTRALIZED CONTROL
7
SemiCENTRALIZED CONTROL
8
Structure of a RTL System
9
Analysis of a RTL System
10
Analysis of a RTL system (cont)?
11
Design of Data Subsystem

• 1. Determine the operators (functional units)?
• -Two operations can be assigned to the same
  functional unit if they form part of diff erent
  groups
• 2. Determine the registers required to store
  operands, results, and intermediate variables
• -Two variables can be assigned to the same
  register if they are active in disjoint time
  intervals

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Design of Data Subsystem (cont)?

• 3. Connect the components by datapaths (wires and
  multiplexers)?
• as required by the transfers in the sequence
• 4. DETERMINE THE CONTROL SIGNALS AND CONDITIONS
  required by the sequence
• 5. DESCRIBE THE STRUCTURE OF THE DATA SECTION by
  a logic diagram, a net list, or a VHDL structural
  description

13
Data SubSystem

• i) STORAGE MODULES
• ii) FUNCTIONAL MODULES (operators)?
• iii) DATAPATHS (switches and wires)?
• iv) CONTROL POINTS
• v) CONDITION POINTS

14
Storage Modules

• INDIVIDUAL REGISTERS, with separate connections
  and controls
• ARRAYS OF REGISTERS, sharing connections and
  controls
• REGISTER FILE
• RANDOM-ACCESS MEMORY (RAM)?
• COMBINATION OF INDIVIDUAL REGISTERS AND ARRAYS
  OF REGISTERS.

15
Register File
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Entity Declaration of Register File

• ENTITY reg_file IS
• GENERIC(n NATURAL16 -- word width
• p NATURAL 8 -- register file size
• k NATURAL 3) -- bits in address
  vector
• PORT (X IN UNSIGNED(n-1 DOWNTO 0) -- input
• WA IN UNSIGNED(k-1 DOWNTO 0) -- write
  address
• RAl IN UNSIGNED(k-1 DOWNTO 0) -- read
  address (left)?
• RAr IN UNSIGNED(k-1 DOWNTO 0) -- read
  address (right)?
• Zl,Zr OUT UNSIGNED(n-1 DOWNTO 0) -- output
  (left,right)?
• Wr IN BIT -- write control signal
• clk IN BIT) -- clock
• END reg_file

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Behavioral Description of Register File

• ARCHITECTURE behavioral OF reg_file IS
• SUBTYPE WordT IS UNSIGNED(n-1 DOWNTO 0)
• TYPE StorageT IS ARRAY(0 TO p-1) OF WordT
• SIGNAL RF StorageT -- reg. file contents
• BEGIN
• PROCESS (clk) -- state transition
• BEGIN
• IF (clk'EVENT AND clk '1') AND (Wr '1')
  THEN
• RF(CONV_INTEGER(WA)) lt X -- write operation
• END IF
• END PROCESS
• PROCESS (RAl,RAr,RF)?
• BEGIN -- output function
• Zl lt RF(CONV_INTEGER(RAl))
• Zr lt RF(CONV_INTEGER(RAr))
• END PROCESS END behavioral

18
Description of RAM Design
19
Entity Declaration of RAM

• ENTITY ram IS
• GENERIC(n NATURAL 16 -- RAM word width
• p NATURAL256 -- RAM size
• k NATURAL 8) -- bits in address vector
• PORT (X IN UNSIGNED(n-1 DOWNTO 0) -- input
  bit-vector
• A IN UNSIGNED(k-1 DOWNTO 0) -- address
  bit-vector
• Z OUT UNSIGNED(n-1 DOWNTO 0) -- output
  bit-vector
• Rd,Wr IN BIT -- control signals
• Clk IN BIT) -- clock signal
• END ram

20
RAM Description

• ARCHITECTURE behavioral OF ram IS
• SUBTYPE WordT IS UNSIGNED(n-1 DOWNTO 0)
• TYPE StorageT IS ARRAY(0 TO p-1) OF WordT
• SIGNAL Memory StorageT -- RAM state
• BEGIN
• PROCESS (Clk) -- state transition
• BEGIN IF (Clk'EVENT AND Clk '1') AND (Wr
  '1') THEN
• Memory(CONV_INTEGER(A)) lt X -- write
  operation
• END IF END PROCESS
• PROCESS (Rd,Memory) -- output function
• BEGIN
• IF (Rd '1') THEN -- read operation
• Z lt Memory(CONV_INTEGER(A))
• END IF END PROCESS END behavioral

21
Functional Modules
22
Data Path

• WIDTH OF DATAPATH
• PARALLEL OR SERIAL
• UNIDIRECTIONAL OR BIDIRECTIONAL
• DEDICATED OR SHARED (bus)?
• DIRECT OR INDIRECT

23
Figure 14.5 EXAMPLES OF DATAPATHS a)
unidirectional dedicated datapath (serial) b)
bidirectional dedicated datapath (parallel)c)
shared datapath (bus).
24
Generalized behavioral Description
25
Interface between Data and control sub system
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Design of control sub system

• 1. DETERMINE THE REGISTER-TRANSFER SEQUENCE
• 2. ASSIGN ONE STATE TO EACH RT-group
• 3. DETERMINE STATE-TRANSITION AND OUTPUT
  FUNCTIONS
• 4. IMPLEMENT THE CORRESPONDING SEQUENTIAL SYSTEM

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CONTROL SUBSYSTEM

• INPUTS control inputs to the system and
  conditions from the data subsystem
• OUTPUTS control signals
• ONE STATE PER STATEMENT IN REGISTER-TRANSFER
  SEQUENCE
• TRANSITION FUNCTION CORRESPONDS TO SEQUENCING
• OUTPUT FOR EACH STATE CORRESPONDS TO
• CONTROL SIGNALS

28
State Assignment

• UNCONDITIONAL only one successor to a state
• CONDITIONAL several possible successors ,
  depending on the value of a condition

29
Moore vs Mealy FSM
30
Design of Multiplier (example)?
31
Entity Declaration of Multiplier
32
Control system of Multiplier
33
Control Sub-system (description)?

• ENTITY multctrl IS
• GENERIC(n NATURAL 16) -- number of bits
• PORT (start IN BIT -- control input
• ldX,ldY,ldZ OUT BIT -- control signals
• shY, clrZ OUT BIT -- control signals
• done OUT BIT -- control output
• clk IN BIT)
• END multctrl

34
Behavior Description

• ARCHITECTURE behavioral OF multctrl IS
• TYPE stateT IS (idle,setup,active)
• SIGNAL state stateT idle
• SIGNAL count NATURAL RANGE 0 TO n-1
• BEGIN
• PROCESS (clk) -- transition function
• BEGIN
• IF (clk'EVENT AND clk '1') THEN
• CASE state IS
• WHEN idle gt IF (start '1') THEN state lt
  setup ELSE state lt idle END IF
• WHEN setup gt state lt active count lt 0
• WHEN active gt IF (count (n-1)) THEN count lt
  0 state lt idle ELSE count lt count1 state
  lt active END IF
• END CASE
• END IF END PROCESS

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Behavioral description (cont..)?

• PROCESS (state,count) -- output function
• VARIABLE controls BitVector(5 DOWNTO 0)
• -- code (ldX,ldY,ldZ,shY,clrZ)?
• BEGIN
• CASE state IS
• WHEN idle gt controls "100000"
• WHEN setup gt controls "011001"
• WHEN active gt controls "000110"
• END CASE
• done lt controls(5)
• ldX lt controls(4) ldY lt controls(3) ldZ lt
  controls(2)
• shY lt controls(1) clrZlt controls(0)
• END PROCESS
• END behavioral