ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 12
• Synthesis of Combinational Logic I

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Synthesis

• Logic synthesis
• Boolean descriptions gt circuits
• RTL synthesis
• RTL descriptions gt Boolean descriptions
• Behavioral synthesis
• Behavioral descriptions gt RTL descriptions

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Objective of Synthesis
Delay
Area
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Logic Synthesis
Behavioral Descriptions
Technology Libraries
Translation Engine
Optimization Engine
Mapping Engine
Technology Implementation
Two-level Logic Functions
Optimized Multi-level Logic Functions
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Translation Engine

• Read in Verilog-based descriptions
• Translate into Boolean equations
• SOP sum of product
• POS product of sum
• A Verilog description consisting only of a
  netlist of combinational primitives without
  feedback can always be synthesized

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Logic Optimization

• Remove redundant logic, exploit logic sharing
• Substitution
• Factoring
• Decomposition
• Extraction
• Elimination/flattening

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Substitution

• Express a Boolean function in terms of its inputs
  and another function
• G a b
• F a b c
• G a b
• F G c

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Factoring

• Find the common factors among a set of functions
• F ac ad bc bd e
• F ( a b ) ( c d ) e
• Two-level gt multi-level
• Area reduced
• Delay increased

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Decomposition

• Express one Boolean function in terms of new
  nodes
• F abc abd acd bcd
• 9 gates, 40 transistors
• F XY XY
• X ab
• Y c d
• 7 gates, 24 transistors
• Figure 8.6, 8.7, page 287

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Extraction

• Express a set of Boolean functions in terms of
  new nodes
• F ( a b ) cd e
• G ( a b ) e
• H cde
• X a b
• Y cd
• F XY e
• G Xe
• H Ye

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Elimination / Flattening

• Remove a node in a function
• Increase area
• Reduce delay
• F Ga Gb
• G c d
• F ac ad bcd

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Combinational Logic Delay
Register Primary Input
Register Primary Output
Combinational Logic
clock

• Combinational logic delay lt clock period

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Synthesis Support to Verilog

• Commonly supported
• Figure 8.17, page 297
• Unsupported
• Figure 8.18, page 298

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Exercise 3
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Find Delay

• module M ( y, a, b, c )
• output y
• input a, b, c
• and (2, 4) (w1, a, b)
• not 3 (w2, c)
• nor (5, 2 ) (y, w1, w2)
• endmodule

a -gt y (9, 4) b -gt y (9, 4) c -gt y (8, 5)
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FSM of Traffic Light Control

• module traffic ( light, clock, pedx )
• input clock, pedx output 10 light
• reg 10 light reg 70 timer
• parameter green 2b01
• parameter yellow 2b10
• parameter red 2b11
• always _at_ ( timer )
• begin if ( timer lt 100 ) light lt green
• else if ( timer lt 110 ) light lt yellow
• else light lt red end
• always _at_ ( posedge clock )
• begin if ( timer lt 130 ) timer lt timer 1
• else timer lt 0 end
• always _at_ ( posedge pedx )
• if ( light green ) timer lt 100
• endmodule