Lecture 8 Digital Chip Design Flow

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Lecture 8Digital Chip Design Flow FPGA
Courtesy RK Brayton (UCB) , A Kuehlmann
(Cadence) And Adnan Aziz from Univ. Texas
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Digital IC Design Types

• Full Custom Design
• Transistor Level Design Custom Layout Spice
  Simulation ( Analog Simulation)
• Standard-Cell Based Design
• Verilog Coding Synthesis Semi Automatic
  Layout
• IP Based Design
• Standard-Cell IPs (CPU Core Etc.)

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Standard-Cell Based Design Flow
Design
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System Level / Functional Level

• Abstract algorithmic description of high-level
  behavior using C, System-C, System-Verilog, etc.
• No implementation details for timing
• Compact execution model as first design draft
• Sometimes hard to maintain throughout project
  because no link to implementation

Void h264_encoder(int image, int bitstream)
static int pixel_data char
add_pixel(pixel_data) ...
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RTL Level

• Cycle accurate model close to the hardware
  implementation

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Gate Level

• Boolean logic using registers and gates with
  delays for gates and wires

1ns
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Gate Level Verilog Code ( Netlist)

• module example ( A, SUM )
• input 90 A
• output 90 SUM
• wire 92 carry
• nr2bd1_hd U748 ( .AN(n475), .B(n476),
  .Y(n473) )
• nr2bd1_hd U749 ( .AN(n480), .B(n481),
  .Y(n478) )
• ivd1_hd U752 ( .A(n2096), .Y(n2122) )
• ivd1_hd U753 ( .A(n2068), .Y(n2094) )
• . . .
• oa21d1_hd U887 ( .A(n1232), .B(n391),
  .C(n1128), .Y(n390) )
• nr2d1_hd U888 ( .A(n497), .B(n498),
  .Y(n495) )
• endmodule

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Gate, Transistor and Layout

• Transistors and wires are laid out as polygons in
  different technology layers such as diffusion,
  poly-silicon, metal, etc.

Gate
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Netlist to Layout
module my_chip ( A, SUM ) input 90 A
output 90 SUM wire 92 carry
nr2bd1_hd U748 ( .AN(n475), .B(n476), .Y(n473)
) nr2bd1_hd U749 ( .AN(n480), .B(n481),
.Y(n478) ) ivd1_hd U752 ( .A(n2096),
.Y(n2122) ) ivd1_hd U753 ( .A(n2068),
.Y(n2094) ) . . . oa21d1_hd U887 (
.A(n1232), .C(n1128), .Y(n390) ) nr2d1_hd
U888 ( .A(n497), .B(n498), .Y(n495) ) endmodule
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ASIC Design Flow
Informal Specification
Logic Synthesis
RTL Spec
RTL Simulation
Gate-level Simulation
Formal Verification
Gate Level Netlist
Static Timing Analysis (STA)
Layout
Manual Changes to fix timing
Modifies Post-Layout Netlist
Test Logic Insertion
Post-layout Simulation
ASIC Foundry
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Informal Specification
RTL Spec
RTL Simulation
Logic Synthesis
Static Timing Analysis (STA)
Gate Level Netlist
FPGA
STA
Layout
Modifies Post-Layout Netlist
ASIC Foundry
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FPGA

• Field Programmable Gate Array
• Programmable device including logic gates, FFs
  and memories.
• Applications are
• End-product
• ASIC Verification

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FPGA Vendors

• Xilinx
• Better density speed, faster compile time
• This is our choice
• Altera
• The following slides are based on Xilinx
  products. But, there is always equivalent
  products from Altera.

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FPGA Types

• ROM type Vertex series
• RAM type Spartan series

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What you should learn above Verilog?

• Programming (Download)
• Pin mapping
• Compile
• Place and Route
• Memory generation
• Clock handling
• Logic Analyzer

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Pinmap Concept

• We need to assign each port from Verilog code to
  a pin of an FPGAgt

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Pinmap Example

• Pin name of each FPGA device is fixed and listed
  on the Xilinx website.
• A user must make a xxx.ucf file to define the
  connectivity between Verilog port and FPGAs pin
  as follows.
• NET a" LOC "P19"
• NET b" LOC "P20"
• NET c" LOC "P21"
• NET f" LOC "P22"
• NET e" LOC "P23"

P19
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Compile, Place Route

• Compile is a process of translating behavioral
  code to gate-level code (netlist).
• Place Route is a process of matching each gate
  from the netlist to a gate of an FPGA.
• A user must specify the pinmap using ucf file in
  PR phace.
• Synplify is an expert compile tool.
• ISE is a tool for compile, PR and everything.

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ISE Compile Result
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Orcad Schematic Sample