Advanced Materials and Structures for Nanoscale CMOS

1
Advanced Materials and Structures for Nanoscale
CMOS

• Prof. Tsu-Jae King
• Department of Electrical Engineering and Computer
  Sciences
• University of California, Berkeley, CA
  94720-1770 USA
• March 29, 2004

2
Outline

• Introduction
• MOSFET scaling
• Advanced Gate-Stack Materials
• Thin-Body MOSFETs
• Summary

3
IC Technology Advancement
Rapid advances in IC technology have been
achieved primarily by scaling down transistor
lateral dimensions
4
Intels 90 nm CMOS Technology

• Used for volume manufacture of
• Pentium and IntelCentrinoTM
• processors on 300 mm wafers
• Lg 50 nm
• Tox 1.2 nm
• Strained Si channel

5
Bulk-Si MOSFET

• Leakage current is the primary barrier to scaling
• To suppress leakage, we need to employ
• Higher body doping ? lower carrier mobility,
  higher junction capacitance, increased junction
  leakage
• Thinner gate dielectric ? higher gate leakage
• Ultra-shallow S/D junctions ? higher Rsd

• Desired characteristics
• High ON current (Idsat)
• Low OFF current

6
SIA Intl Technology Roadmap for Semiconductors
(2003)
Year 2004 2005 2006 2007 2010 2013 2016
Technology Node 90 nm 80 nm 70 nm 65 nm 45 nm 32 nm 22 nm
Tox
Idsat
Solutions Being Pursued
No Known Solutions
7
Approaching 1.4 nm Tox,inv

• Use high-k gate dielectric (by 2007)
• Thicker physical thickness for given Cgate
  (F/cm2)
• -gt lower gate leakage current
• HfO2 is a promising candidate
• Issues ? Thermal stability
• ? Interfacial SiO2 layer -gt increased
  Tox,inv
• - may be needed for good mobilities
• Reduce/eliminate gate depletion effect
• Poly-SiGe or metal (by 2007?)
• Issues ? Process compatibility
• ? Work function

8
Achieving Low Rsd

• Increase source/drain dopant concentration
• Issue ? Ultra-shallow junction formation
• Use elevated source/drain structure
• Issue ? Process complexity
• Lower source/drain contact resistance
• Issue ? New materials / process complexity

9
Outline

• Introduction
• Advanced Gate-Stack Materials
• Poly-SiGe gate electrode
• Mo gate electrode
• Thin-Body MOSFETs
• Summary

10
Poly-Si Gate Technology Issues

• Gate depletion effect
• reduced Idsat Cox(Vdd-Vt)

• Boron penetration
• Vt variation
• degraded gate-dielectric reliability
• Gate resistance
• Remote charge scattering
• reduced carrier mobilities (M. Krishnan et al.,
  IEDM 1998)
• Stability on high-k gate dielectrics

11
Why Poly-SiGe Gate?

• Advantages
• Reduced gate depletion effect (GDE)
• Less boron penetration through gate oxide
• Straightforward process integration
• Work functions are appropriate
• N poly-SiGe gate for NMOS
• P poly-SiGe gate for PMOS
• Optimal Ge content 20
• (W.-C. Lee et al., IEEE Electron Device Letters,
  Vol. 19, p. 247, 1998)
• Poly-SiGe on high-k gate dielectric?

12
Poly-SiGe/HfO2 MOSFET
Q. Lu et al., 2002 Symposium on VLSI Technology

• PVD HfO2 at UT Austin
• Prof. Jack Lees group
• Conventional CMOS process flow
• 800oC, 30m furnace anneal 1000oC, 10 sec RTA

• Poly-SiGe gate yields lower Tox (EOT)!
• Low gate leakage current maintained

13
Poly-SiGe/HfO2 Gate Stack

• Interfacial layer eliminated!
• EOT reduction similar to that achieved with
  surface nitridation (SN)
• SN -gt degraded mobilities
• Promising for low EOT with low leakage, good
  mobilities (?)

14
Metal Gate Technology

• Required properties
• Appropriate work function
• High Tm (gt1000?C)
• Stable interface with gate dielectric
• Compatible with Si processing deposition, etch
• Candidate materials
• High-Tm metals (Ta, Mo, Ru, W)
• metal nitrides (MoN, WN, TiN, TaN)
• doped metal oxides (In2O3, SnO2, RuO2)
• metal silicides (CrSi, WSix)

15
Dual-Work-Function MetalGate Technology

• Possible approaches
• Deposit etch 1st metal deposit etch 2nd
  metal
• (Q. Lu et al., 2000 Symposium on VLSI
  Technology)
• exposes gate-dielectric to etch process
• Deposit 1st 2nd metals selectively remove 2nd
  metal anneal to interdiffuse or alloy metals
• (I. Polishchuk et al., 2001 MRS Spring Meeting)
• Deposit one metal selectively adjust FM
• (Q. Lu et al., 2001 Symposium on VLSI Technology)

16
Why Mo Gate?

• Advantages (vs. other metals)
• Compatible with conventional process flow
  sequence
• stable on high-k gate dielectrics (Q. Lu et al.,
  2001 Symp. VLSI Tech.)
• Work function can be tuned by incorporating
  nitrogen
• Impact on gate dielectric can be minimized
• Damageless sputtering of Mo
• H. Takeuchi et al., DRC 2003
• Diffusion of N into Mo from TiN1x cap
• R.J.P. Lander et al., MRS 2002 Spring
  Meeting
• Tilted N implantation into Mo
• T. Amada et al., MRS 2002 Spring Meeting

17
FM Tuning by Ion ImplantationP. Ranade et al.,
IEDM 2002

• FM can be lowered by N implantation and thermal
  anneal
• DFM increases with
• dose
• energy
• (N segregates to SiO2
• interface forms Mo2N)

18
FM Variation with Gate Dielectric
19
The Metal-Dielectric Interface Intrinsic States
and Dipole Formation
20
Effective FM of Metal Gate
For low-FM gate FM,eff gt FM,vac
21
Implications for FM,vac Requirements

• Pinning effect is larger for high-k dielectrics
• To get desired FM,eff on high-k gate dielectric
• even smaller FM,vac is needed for NMOS
• even larger FM,vac is needed for PMOS

22
Outline

• Introduction
• Advanced Gate-Stack Materials
• Thin-Body MOSFETs
• Ultra-thin body
• Double-gate
• Summary

23
Thin-Body SOI MOSFETs(by 2007?)
Ultra-Thin Body
Double Gate
Common feature A thin body, such that no
conduction path is far from the gate
24
Ultra-Thin-Body MOSFET

• Lg 12 nm
• Tox 2 nm

• UTB suppresses leakage
• Thick S/D gt low Rseries

M. Takamiya et al., Proc. 1997 ISDRS, p. 215
B. Yu et al., Proc. 1997 ISDRS, p. 623
25
20 nm Lg UTB CMOSFETs
Krivokapic et al. (AMD), presented at the Intl
Conference on Solid-State Devices and Materials
(Tokyo, Japan) Sep. 03.

• TSi 6 nm
• Tox 1.3 nm (SiO2/Si3N4)
• Strained Si channel

• Excellent Idsat achieved with thick S/D structure

26
UTB MOSFET Scaling

• Issues for bulk-Si MOSFET scaling obviated
• Body does not need to be heavily doped
• Tox does not need to be scaled as aggressively
• Ultra-shallow S/D junction formation is not an
  issue
• Body thickness must be less than 1/3 x Lg
• Formation of uniformly thin body is primary
  challenge
• For TSi lt 4 nm, quantum confinement interface
  roughness ? VT variation and degraded gm
• K. Uchida et al., IEDM 2002

27
Double-Gate FinFET

• Self-aligned gates straddle thin silicon fin
• Current flows parallel to wafer surface

Gate
Drain
Source
28
15 nm Lg FinFETs
Lg
DRAIN
GATE
20 nm
DRAIN
GATE
TSi
10 nm
Lg lt 20 nm TSi 10 nm Tox 2.1 nm
SOURCE
SOURCE
Sub-Threshold Characteristics
Output Characteristics
Y.-K. Choi et al., IEDM Technical Digest, pp.
421-424, 2001
29
10 nm Lg FinFETs
B. Yu et al., IEDM Technical Digest, pp. 251-254,
2002
30
FinFET Scaling

• Compared with UTB-MOSFET
• Reduced short-channel effects gt more scalable
• Higher current drive due to
• steeper subthreshold swing (60 mV/dec)
• lower channel electric field gt higher carrier
  mobilities
• Fin width must be less than 2/3 x Lgate
• Formation of narrow fin is primary challenge
• sub-lithographic process needed

31
Reducing Gate Leakage

• DG-MOSFET provides lower Ig
• Tox can be more aggressively scaled (improved
  Idsat)

L. Chang et al., IEDM 2001
32
Selective Deposition of Ge

• Conventional LPCVD tool
• GeH4 gas, 340oC, 300mT
• Ge deposits selectively onto Si

33
FinFET with Raised Ge S/D

• Ge can be selectively deposited on top of Si
  fin(s)

34
Why SiGe for S/D Contacts?

• Lower resistivity than Si (for p doping)
• Selective deposition onto Si is easy
• thicker S/D contact regions ? lower Rsd
• Low specific contact resistivity
• smaller bandgap
• ? smaller Schottky barrier

rc 10-8 W-cm2 for germanosilicides on
SiGe Prof. Ozturks group at NCSU gt meets ITRS
requirement!
35
Idsat Improvement w/ Raised S/D
Lgate 90 nm Wfin 70 nm W 2 x Hfin 100 nm

• Additional process steps
• Remove SiO2 over S/D
• Selectively grow 70 nm Ge
• Implant dopants
• 750oC activation anneal
• 400oC FGA
• 28 improvement in Idsat

w/ Ge
w/o Ge
Ge offers low thermal processing budget for S/D
formation - useful for advanced gate-stack
materials
36
Circuit Performance Comparison

• No channel doping is needed in thin-body FETs
• higher Idsat achieved, dopant fluctuation
  effects avoided

37
Molybdenum-Gated FinFETs
Y.-K. Choi et al., 2002 IEDM
S
N
Poly-Si
N
Mo
D
W
Lgate
Tbody

• Tilted N implantation (60?) used for sidewall
  gates
• N implantation lowers gate work function

• Tilted N implantation (60?) used for sidewall
  gates

38
Impact of S/D Contact Structure
H. Kam and T.-J. King, to be presented at the
2004 Silicon Nanoelectronics Workshop
Top Contact
Wrapped Contact
3D simulated Id-Vds curves
Lg18nm, Wfin10nm, Tox5A
End Contact

• Contact resistance will limit Idsat
• ? maximize Acontact , minimize rc
• wrapped contact structure
• (germano)silicided thick S/D

rc10-9 W-cm2
39
Minimizing Parasitic Resistance

• Use thin-body structure to control leakage
• Use metallic source/drain to minimize Rseries
• e.g. fully silicided source/drain regions
• Ideally, Schottky barrier height Fb ? 0 eV

40
Thin-Body Metallic-S/D MOSFETs
J. Kedzierski et al., IEDM Technical Digest, pp.
57-60, 2000

• TSi ? 10nm
• PtSi (Fbop0.24V) for PMOS
• ErSi1.7 (Fbon0.28V) for NMOS
• Excellent IOFF
• High NMOS contact resistance due to oxidation of
  ErSi1.7

41
Outline

• Introduction
• Advanced Gate-Stack Materials
• Thin-Body MOSFETs
• Summary

42
Summary

• Advanced materials are needed for bulk-Si MOSFETs
  to meet ITRS specifications
• High-k gate dielectric
• Poly-SiGe and eventually metallic gate electrodes
• Raised S/D structure (SiGe for low Rsd)
• Thin-body MOSFETs provide pathway to 22 nm (9nm
  Lgate) technology node
• High-k gate dielectric will not be necessary
• Metal gate and low-Rsd materials will be needed

43
MOSFET Scaling Scenario
Lg (nm) 65 50 40 30 20
10