Nanocomputing technologies

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Nanocomputing technologies

• José A. B. Fortes
• Dpt. of Electrical and Computer Eng. and
• Dpt. of Computer and Information Sci. and Eng.
• University of Florida, Gainesville
• fortes_at_ufl.edu

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Nanocomputing

• Computing with nanoscale devices
• 1 nm 10-3 µm width of 10 H atoms diameter
  of sugar molecule
• 1011- 1012 devices/cm2
• 100 1000 billion-device chips
• 1 50 nanometer device features
• CMOS faces difficult challenges above 65 nm and
  extremely hard/expensive ones below 65 nm
  (SourceITRS)

Year 2001 2004 2007 2010 2013 2016
DRAM½ Pitch 130 90 65 45 32 22

• Ggate, Gbit, GHz bottom-up built FPGA/RAM
  nanoarrays by 2010-2015

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Nanotechnology A Convergence of Enabling
Technologies
Dimension (nm)
Microelectronics
Building
100 ?m
10 ?m
Downscaling
Biological Cell
Device Dimension in CMOS
1 ?m
Optical Microscopy
Gate Length in CMOS
100 nm
10 nm
Nanoclusters
Oxide Thickness in CMOS
1 nm
Simple Molecules
Imaging/Manipulation of Structures
Electron Microscopy
0.1nm
Atoms
Scanning Probes
Chemical/Biological Synthesis
This slide provided by D. Janes
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Towards nanoscale CMOS

• Transistor gate scaling

silicide
Strained Si
Intel Aug 02, Spectrum Oct 02, 02 International
Electron Devices Meeting (IEDM), Dec 02
www.intel.com/research/silicon/90nm_press_briefin
g-technical.htm
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Barriers to CMOS as usual
Source G. Bourianoff
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Many challenges

• MOS PERFORMANCE AND LEAKAGE PROCESS INTEGRATION,
  DEVICES, AND STRUCTURES
• PRODUCTION OF NON-CLASSICAL CMOS FRONT END
  PROCESSES
• POWER MANAGEMENT DESIGN
• HIGH-SPEED DEVICE INTERFACES TEST AND TEST
  EQUIPMENT
• COORDINATED DESIGN TOOLS AND SIMULATORS TO
  ADDRESS CHIP, PACKAGE, AND SUBSTRATE CODESIGN
  ASSEMBLY AND PACKAGING

Source ITRS 2001
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Meindls perspective (1)

• Hierarchy of physical limits
• fundamental, material, device, circuit, system
• System Architecture, switching energy, heat
  removal, clock frequency and chip size
• potential for TSI
• gt 1 trillion transistors/chip
• 2-gate transistor, 10-nm/3-nm channel
  length/thickness, 1-nm gate oxide

Science, vol. 293, Sep 2001
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Meindls perspective (2)

• Wire vs. transistor in state-of-the-art 100-nm
  technology
• 6 times the latency, 5 times the energy

• Tyranny of interconnects
• Equal latency for superconductive 30-mm
  interconnect with vacuum insulator and 10-nm
  transistor
• Larger switching energy

• Moores law to continue via interconnect
  improvements
• Better-than-silicon technologies must be
  interconnect centric

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System design challenges

• Vanishing design spaces for existing paradigms
• and revolutionary technologies that may not be
  well suited for conventional logic and
  architectures
• Interconnect-limited performance
• Local connections desirable but not enough
• A function of how system uses interconnect

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Emerging technologies

• Nanocomputing taxonomy

Source The future of nanocomputing, G.
Bourianoff, Computer , 8/03
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Builders versus Chiselers a Historical View
Chiseling Start with a relatively uniform,
large piece of material --selectively
shape/remove material to define desired object.
Building Start with small building blocks
combine and arrange them to form interesting
assemblies
This slide provided by D. Janes
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Builders versus Chiselers -- Micron to Atomic
Scale
Nanoclusters Molecules
Si Substrate
Ag
Au
X
X
Lithography, etching, implant
Y
Self-Assembly
Au
Structure
Ag
PMOS device
NMOS device
Chiseling Use lithography, etching, etc. to
define devices, interconnects Yields well
optimized device structures, nearly arbitrary
interconnect configurations
Building Use chemical affinities, etc. to form
controlled assemblies of atoms, molecules,
clusters Potentially fast, flexible, able to
generate nanometer scale structures
This slide provided by D. Janes