Prof' Rao R' Tummala

1
Greetings from Georgia Tech PRC
EmergingTrend From
ICs

• Prof. Rao R. Tummala
• Joseph M. Pettit Endowed Chair Professor in ECE
  MSE Director, 3D Microsystems Packaging
  Research Center
• Georgia Institute of Technology Atlanta, GA USA

2
3D Systems Executive Summary

• Devices cannot be used until packaged
• Packaging is highly interdisciplinary
• Packaging limits systems functionality and cost
• Engineering Limits to CMOS ICs are foreseen
• Engineering limits with organic substrates are
  foreseen
• 3D ICs are viewed as a potential Solution
• ICs and 3D ICs are small part of any system
• 3D Systems is the holy-grail for quantum jump
  in Functional Density at lowest cost in smallest
  size

3
Key Themes

• Summary of Progress in ICs and 3D ICs
• 3D Systems Vision _at_ GT PRC
• Recent Progress in 3D Systems

4
The Inter-disciplinarity of Packaging

• Mechanical Sciences
• Efficient and cost effective thermal transfer
• Interfacical stresses
• Fatique
• Warpage
• Creep

• Electrical Sciences
• Low impedance power feed
• Low inductance/high capacitance
• Cross talk
• Attenuation

• Material Sciences
• Dielectrics
• Conductors
• C,L,R,Antennas
• Multilayer structures

• Chemical Sciences
• Lithographic processes
• Microstructure development

5
Current Approach to Systems
1. ProcessorPackage
3. Discrete Components
2. Stacked Memory
4. Connectors Batteries
6
Need for 3D Systems to Eliminate the Gap
108
107
106
105
Transistors/cm3
Component Density cm3
Gap105 x
104
System Integration Law
103
102
10
1971
1980
2000
2020
1990
Sources IBM, Intel
7
IC Vs Package Vs System Miniaturization
250,000
200,000
100,000
20,000
Lithographic Dimension (nm)
4,000
2,000
0
1980
1990
2000
2010
1970
8
Can we miniaturize the entire system?
9
ICs to Systems and Applications

• CMOS IC to 22nm
• Module by 3D ICs with TSV
• System by 3D Systems with TPV

10
3D System Drivers and Technologies Necessary
3D SYSTEMS
3DSystems
11
3 Barriers to Systems
Wafer
IC PACKAGING
System Interconnects
Board
Discretes
SYSTEM PACKAGING
12
Georgia Tech-PRC Vision of 3D Systems

• 3D SYSTEMS
• Consumer
• Energy
• Automotive
• Healthcare
• Computer

Passives R, L, C, Antennas Packages
and Boards Thermal Materials and Interfaces
Power Sources System Interconnections
Reliability System Design Tools
13
Why Miniaturize?

• Miniaturization leads to
• Lower Cost
• Higher Performance
• Higher Reliability
• Higher Functionality
• Examples
• ICS from 1 micron to 32 nm
• WB to FC to TSV
• Ceramic to Organic
• PTH to SMT

14
ICs

• IC integration continues
• Most ICs are commodities
• Performance beyond 32 nm is limited
• Integration of dissimilar ICs expensive
• Wafer fab investments very high
• Design technology issues
• Future uncertain beyond 32-22 nm

15
Why 3D ICs?

• Design efficiency
• Heterogeneous ICs
• Higher chip yield vs. large SOC
• Logic-SOA
• Analog -- past generation
• Low interconnect delay
• Higher bandwidth
• Less power
• Miniaturization
• Faster time to market

Ultimately Lower Cost
16
Historical Evolution of 3D Packaging ICs
SIP Si Substrate Technologies
1970
1980
2000
2010
Year
17
3D Packaging 3D IC Evolution
Recent
Past
Emerging
Chip Stack by TSV Bosch, TruSi etc.
Chip Stack by Wirebonding ChipPac
Piggyback DIP IBM, 1973
ASET Si Thru Via
POP Chip Stack Sharp
Ultra Thin W2W and D2W Stacking IBM, Tohoku
Univ, DARPA VISA, IMEC etc.
POP
Stacked TSOP DST Modules, Inc.
POP Chip-on-Chip IMEC
Ultra Thin RF modules by EMAP by GT PRC
18
3D Packaging in Cell Phones

• 3D ICs with Wire bonds

• Package on Package (PoP)

19
3D IC 3D System Applications
2008 2010 2012 2014
Courtesy of MCNC
20
3 Types of TSVs

• TSV as an interconnection CIS
• TSV in 3D with similar ICs to improve density
  Memory
• Cost of TSV vs. WB
• Beyond 64GB Chip
• TSV in 3D with dissimilar ICs to replace SOC
• Impacts FEOL and BEOL
• Partitioning of system

21
Georgia Tech-PRC Vision of 3D Systems

• 3D SYSTEMS
• Consumer
• Energy
• Automotive
• Healthcare
• Computer

Passives R, L, C, Antennas Packages
and Boards Thermal Materials and Interfaces
Power Sources System Interconnections
Reliability System Design Tools
22
Miniaturization Trend to 3D Systems
Laptop
SINGLE FUNCTION
Functional Density or Component Density / cm3)
Cellular
MULTI -FUNCTION
23
Two Types of Components

• Device Components
• 10 of System
• System Components
• 90 of Systems

24
Limits of Organic Wafer Level Packaging

• Organic substrate Challenges
• Dimensional stability
• Lower I/Os
• Higher cost
• WLP
• Low I/Os
• High Cost

25
3D and Embedded Packaging in Upcoming Wireless
Systems

• 1. Package-on-Package (PoP)

2A. Embedded Die
2B. Fan-out Wafer LevelPackaging
3. Chip-Last Ultra-thin3D EMAP
Sources Amkor, Georgia Tech, Infineon, Imbera,
ST Micro, Stats
26
Packaging Technology Trend to 3D Systems
Sources Infineon, Georgia, Tech, Stats, ST
Ericsson
27
Chip-last Embedded MEMS, Actives Passives _at_GT?
28
3D-System Partitioning
29
Single Technology Platform for Systems-3D ASSM
ICs and 3D ICs

3D Systems
Sources IBM, Intel
30
GTs Strategy for 3D Systems
31
3D Systems Research _at_GT PRC at or Close to
Nanoscale

• Glass and NT-Si Interposer
• Low-cost Focus
• Low cost TPV in Glass and Si
• Nanoscale 3D System Research Examples
• Sensors
• Capacitors
• Thermal Materials interfaces
• Interconnections

32
3D Systems Start With Low-Cost 3D Interposer
5 µm
5 µm
10µm
5 µm
Si/Glass Core
100- 200µm
5µm
Metallization (Cu)
Polymer buffer layer
Adhesion/Barrier Layer/Liner

• Through Via Diameter 20-50µm
• Blind Via diameter 15-25µm
• Pad size Via diameter 10 µm
• Line/Space 5µm/5µm

33
Why 3D Glass or Si Interposers?
Limitations Shown in Red
34
Lower-cost TPV Processes at GT PRC
Filled TPVs
Bottom-up Plating
Double-Sided Plating
Top-Down View Cross-Sectional View
35
Through- Package Vias in Thin Glass Core
CO2 Laser Ablation

• Borosilicate Glass (175µm Thickness)
• Via Formation
• Laser Ablation (CO2, UV, Excimer)
• Mechanical Drilling
• Polymer Buffer Layer
• Laminated dry film
• Metallization
• Seed layer Ti/Cu Sputtering or Electroless
  plating
• Via Fill Electroplated Cu

Entrance
Glass
175µm
Entrance f - 100µm Exit f - 50µm Pitch
- 175µm
Exit
10x magnification
36
TPV Modeling Glass vs. Si
30 um
30 um
TPV
TPV
100 um
100 um
Silicon
Glass
Si
EM Model
Polymer or SiO2 Liner
Glass
Si 10ohm-cm, 5um polymer liner
S21 (dB)
Si 10ohm-cm, 0.1um SiO2 liner
37
Filter Glass. vs. Si
3D View of a Filter
Filter Schematic
38
TPV Reliability Stress Analysis in Cu-Filled TPV
E Youngs modulus n Poisson ratio
39
Basis of low-cost of 3D Systems

• Large wafer or Panel
• Miniaturized components
• Low cost materials and processes
• High throughput tools

200-300 mm Wafer
600 mm System-On-Panel
40
Nano-materials as the Basis for 3D Systems
41
Trend to Nano-decoupling Capacitor

• High Surface Area Nanoelectrodes
• Thinner dielectrics
• Stable properties with frequency
• Take Advantage of New PolarizationMechanisms
• Interfacial polarization
• Electrical double layer type polarization

42
Thermal Materials and Interfaces
43
Metallizable CNT

• CNT carpets (30006000 W/mK) as TIM
• Patterned growth of CNTs
• Transfer and assemble lt200C
• Decrease the thermal contact resistance

44
Chip-to-Package Interconnections
ADVANCED FLIP CHIP
ADVANCED PAD-TO-PAD BONDING
NANOADHESIVE BASED FINE PITCH COPPER BONDING

• Polymeric adhesive with metal nanoparticles
• More tolerant to planarity and warpage
• Process for reliability in HAST, HTS, TCT

• Lead free solder
• Copper bump interconnections
• Nanocopper and nanocomposite solders
• 50-100 micron pitch

THIN FILM AND NANOMETALLIC BONDING
Nanocomposite solders
Nano Silver bonding layer

• Thin intermetallic bonding Low temp. Cu-Cu
  bonding

45
Fatigue of Nanoscale Materials
Experimental Data from Nanocopper and Microcopper
10-3
450
Crack growth rate (mm/cycle)
Nano Cu
Micro Cu
Stress Amplitude (MPa)
10-4
300
Nano Cu
10-5
150
Finegrain Cu
Micro Cu
10-6
0
2.0x107
100
0.5 x104
1.0 x 106
10
DK Measure of stress intensity at crack tip
(MPa vm)
Number of Cycles
Sources Shubhra Bansal, Georgia Tech
46
PRC Focus ZnO Nanowire Sensors

• ZnO Nanowire / Nanobelt
• Wideband gap semiconductor
• Piezoelectric material
• Bio-compatible material
• The applications of this detection system include
  early detection of breast cancer, food and drink
  pathogens such as E. coli and Salmonella.

47
Global Industry Consortium by GT
48
Summary

• System miniaturization by 3D systems allows
  disruptive functionality beyond 3D ICs
• Low-cost 3D-Interposer is starting point for 3D
  systems
• Novel thin film and nano-technologies provide the
  necessary breakthroughs to 3D systems
• Georgia Tech to launch Industry-University
  Consortia in
• Low cost 3D Glass Silicon Interposer
• Embedded Mems, actives and passives with
  chip-last interconnections with chip-first
  benefits