Verilog???? ? ? ? ? ??????????????

1
Verilog????? ? ? ???????????????
2
1.??????????? ???????????????
????????????seminar???????????
????Verilog?????????????????? (DOS/V???) C?semin
ar?Verilog (98???) A?seminar?Verilog ???Verilog
????????????Verilog???????? ??????????????????????
???
3
2.Verilog???????
??1 aoi??? aoi.v module aoi(a,b,c,d,f) input
a,b,c,d output f assign f((a b)(c
d)) endmodule
4
(1)verilog?????????????? (2)???????????module?????
,endmodule????? (3)?????module??????????(??????)
????? (4)????????????????????????? ? ?
input ? ? output ??? inout (5)??????endmodul
e????????????????? endmodule?????????????
(6)????????,?????assign????????? assign ??
?? (7)Verilog????????,C?????? AND ??????P64
?3.2 OR NOT EX-OR (8)????????( )???????
5
?????????QuickWorks
???????SpDE ? ?????
????? SYNARIO
???? Synplify
Verilog?????? SILOS?
Verilog??
VHDL??
HDL???? ??????
6
3.SpDE??? ???? - ????? - QuickLogic ?
SpDE? SpDE???????
7
4.HDL???????
SpDE?????????HDL????????? ? ????HDL?????????????
????? ????
8
5.Verilog????????? ??1?Verilog????????File?SaveA
s?????? ?seminar?verilog?????????aoi.v??????
?????????module?input???Verilog????? ?????????????
??????????HDL????? Window?Colors?Keyword ???????
?????? File-Exit?HDL?????????SpDE?????? 6.????Sy
nplify??? Spde?File-Import-Verilog?????? ?seminar
?verilog?aoi.v????????????? ??????
9
7.????????????????? RUN????????Change???????? Par
t?p8x12b?Package?pl44?????OK?????? ???RUN?????????
?????????
10
8.?????? ??????????????????????????? ViewLog?????
???????????Edit???? ????HDL???????????????????????
11
9.????????????? ????????Done?????????????????? ??
?????????????????????SpDE??????
12
10.??????? SpDE????????RunTools????
????? ??????????????RUN?????????????
13
11.????????? SpDE???????FullFit????
????? ?????????????
14
???View-NormalFit?????????Z????? ????????????????
???????????? ??????????ZoomIn???? ??????
15
???????????????????????? ?????????rspsq??????
??????? ab1???cd1?? f0 ??????
f1 ???????Verilog?????????????????? ???????
s
f
p
b
r
a
q
??s ??r 0 p 1 q
?????????????? File-Save???????? ??????
d
c
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12.??????(??) HDL?????????aoi.v????????????
module aoi(a,b,c,d,f) input a,b,c,d output
f // assign f((a b)(c d)) wire
ab,cd,o assign aba b assign cdc
d assign o ab cd assign f o endmodule
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(1)??????????????,wire????? ????????????????
ab,cd,o (2)1?????wire????????????????
??????????wire??????? (3)//?1??????????
/?????/????????????????? ??????????????????????
????? ????????????????????????
18
??1 ?????LS04.v??????????????? ??2
NAND???LS00.v??????????????? ??3
NOR???LS02.v???????????????
19
13.???? ??2 ??????? mux2.v include
"aoi.v" module inv(a,f) input a output
f assign fa endmodule module
mux2(sel,a,b,f) input sel,a,b output f inv
g1 (sel,selb) aoi g2 (sel,a,selb,b,fb) inv g3
(.a(fb),.f(f)) endmodule
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(1)???????????????????? (2) ?????,???????????
??????????????? (3) ???????????,
inv???,???????????????, aoi???,?????????,in
clude?????? (4) ????????????,???????????????,
?????? ???????(??????)
????????????,g1,g2,g3?????????
21
(5) ???????????????????????????
???????????????, g1,g2???,????????????
g3???,???????????? (6) ??????????????????????
(7) ?????selb?fb?,???????wire???? ?
????????????? DOSV?? shift _at_ 98
?? shift shift 7 ??????????
22
??2????????????????????? ??????????????1???????? ?
?????????? sel1?? fa sel0?? fb ????????
b
a
sel
f
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14.????assign? ??3 ???? mux21.v module
mux21(sel,a,b,f) input sel,a,b output
f assign fsel ? ab endmodule
mux21
sel
a
f
b
(1) ??2(mux2.v)?????????????,???????
???,??????????????????? (2)assign???C???3????(????
?????)??? ????assign????, assign ??(???1) ?
(??1) (??2) ????? (3)?????,sel1??fa,sel0?
?fb????
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15.always??if? ??3 ???? mux21.v module
mux21(sel,a,b,f) input sel,a,b output
f reg f always_at_(sel or a or b)
begin if(sel1'b1) fa else fb end
endmodule
mux21
sel
a
f
b
(1)3???????,??????if?????, module-endmodule??,??
???????????? ???????,always????????????
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(2)always?? always_at_(???) begin end
????????????? ??????,( )??????????????????????
???,( )???always?????????????????? ??????????????
????? ????????????,??????? or??????????
(3)always?????????????????,????? ??????????????
???????????? (????????????????)
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(4)always???????,if?,case????, if(???) ?1 else
?2 ??????if?????? if(???1) ?1 else
if(???2) ?2 else
?3 (5)????????????C?????? ??? gt ? gt
?? ! ????? lt ? lt ?? ???,??,????????
??? ??? ! ???? ????? (6)1????????
1,0,1'b1,1'b0 ???? ' ?SHIFT7???
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(7)???????,always??????? ??????,assign?????????
????????????,?????? ???????????? ?????????
f ???????? (8)??????????,??????????????
??????????????????????,?????? ???????????????????
??????? (9)if????????????????,???,
if????else????,??????, ???????,??????????? ??3?
???????????????????? ?????2?????????
28
Verilog????? ????????? ??????????????
29
1.???????????? ??3???mux21.v??Verilog??????????
?????? ??????????????????Verilog??????? ???????
?????????????? .tf ?????? HDL?????mux21.v????????
HDL? GenerateTestBench ???????????????????mux21.
tf???????? (????????????????????) (1) timescale
1ns/1ns (2) module t (3) reg sel,a,b (4) wire
f (5) mux21 m (.sel(sel),.a(a),.b(b),.f(f))
(6) // Enter fixture code here (7) endmodule
// t
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(1)timescale???????????????????????
/??????????????????????? /?????????????????????
?? ???????????????1ns?????? (2)????????????????
??????????????? ?????????????????????? t
??? (3)????????????????????????????
??????????????? (4)???????????????????????? (5)?
?????????????????????????????
????????????????????????? ??????????????? (6)??
?????????????????????????
31
timescale 1ns/1ns module t reg sel,a,b wire
f mux21 m (.sel(sel),.a(a),.b(b),.f(f))
// Enter fixture code here initial begin
sel0 a0 b0 100 sel0 a0 b1 100
sel0 a1 b0 100 sel0 a1 b1 100
sel1 a0 b0 100 sel1 a0 b1 100
sel1 a1 b0 100 sel1 a1
b1 end endmodule // t
?????6?????? ???????????? ????????????? ?????mux
21.tf??? ???????? ?????????????? ??????????????
???initial???????? ??????? sel,a,b??????? ??0????
???100ns ???????????????
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2.??????????(Pre-Layout) (1)SpDE??????????????????
?? ? ????SILOS3??????? ????????????Pre-Layout??
????? ??????????mux21.tf? ????????????mux21.v?????
???? ????OK????????
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(2)mux21.v??????????????????? ??????????mux21.tf??
??? ???????output???????????????????? ???????????
???????????? output???????????????(4)??????
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(3)?????????????SILOS3?File?Open???? ??mux21.tf???
?????????????? ?????????SILOS3?File-Save????? mu
x21.tf?????????????? ??????????
Load/Reload???? ??????????SILOS3? ???????
output???????????????GO???? ? ???(4)??????
output?????????????????????????? ?????????mux21.tf
??????????? ??????????
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(4)????????????????????????????? ?????????????1000
ns?????OK??????
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(5)?????????output?????? 32 State changes on
observable nets. Simulation stopped at the end of
time 1.000us.???????? ?????????????
?????????????? ??????
37
???????????????????? ????? tt?a,b,f,sel????????
??????? AddSignaltoAnalyzer???????????????
38
????????????????????????? View-ZoomAll??????????
??????? sel0??fb? sel1??fa???????
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(1)?????????????????????????????? timescale??????
??????????????????? ????????? (2)????????????????
?????1????? ?????????????2??????????????? ????????
???????T1,T2,Tdelta???????? (3)?????????????????
??? ? ????????????????????????
?????????????a,b,sel?????f????? ????????Tdelta0??
???? ????????????????????????????? ??????????(Pr
e Layout)???????? ?????????SILO3?File-Exit???????
????? ?????????
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3.??????????(Post-Layout) ??SpDE?????????????????
??? ? ????SILOS3??????? ???????????????Post-Lay
out??????? ??????????mux21.tf? SDF?mux21.sdf? ????
????????mux21.vq ????????? ????OK????????
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1000ns?????OK??????
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output??????92 State changes on observable
nets. Simulation stopped at the end of time
1000.000ns.?????? ????????????????????????????? ??
?????????? ?????????????
43
(1)?????????????????????1????? ?????????????2?????
?????????? ???????????????T1,T2,Tdelta???????? (2
)????????????????????
? ???????????????????????? ?????????????a,b,sel??
???f????? ???????????Tdelta9ns??????????
??????????????????????(mux21.sdf) ???????????????(
Post Layout)???????? ???Verilog??????mux21.v?????
??????? ?????mux21.vq?????????? SDF?????????????
??????????????? ??????????? ?????????SILO3?File-E
xit?????????? ???????.sdf?.vq???????????????
44
?????????????
45

??4 ?????LS04.v?????????????
?????????????????????? ??????? ??5
NAND???LS00.v?????????????
?????????????????????? ??????? ??6
NOR???LS02.v????????????? ???????????????????
??? ???????
46
4.??????? ??????????????????????????? ???????????
?????????????????? ?????????????????????????????
??????????????????????????????
SpDE?Tools-Options???????BackAnnotation?? ?????Fix
Placement?IOcells?????on?????
47
OK?????RunTools???? ?????????? ????????????mux2
1.scp???????? ?????16,17,18,19??????????????? ???
?(???????????????????) ?????ql_placement??????????
???????? mux21.scp Synplicity Synthesis pin
location command file Automatically generated by
SpDE version SpDE 7.0 Date 8/10/98 at
1002 ---Fixed I/O cells--- portprop f
ql_placement"IO2" portprop a
ql_placement"IO3" portprop sel
ql_placement"IO4" portprop b
ql_placement"IO5"
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????Synplify???????Add????????? ????????PropertyF
iles(.sc)???? mux21.scp???????????????
49
SourceFiles?mux21.scp????????????? RUN???????????
??? ???????OK???????mux21.scp????? ??????????????
????
50
Verilog????? ? ? ???????????????
51
1.???????????? ??1 ?????? comp.v module
comp(a,b,eq,ge,le) parameter n4 input n-10
a,b output eq,ge,le reg eq,ge,le always_at_(a or
b) begin if(ab) eq1 else eq0 if(agtb)
ge1 else ge0 if(altb) le1 else
le0 end endmodule
ge
4
comp
a
eq
4
le
b
52
(1)????1???????????????, ??????????????input,out
put???? MSBLSB ???,??? ???????
??????,???????????1???????? 150 81 11
6 07 ?????????MSB,LSB???????????,
???MSB,???LSB???? (2)????????????????parameter???
???????
53
??1??? module comp(a,b,eq,ge,le) parameter
n4 input n-10 a,b output eq,ge,le assign
eq(ab) assign ge(agtb) assign
le(altb) endmodule
ge
4
comp
a
eq
4
le
b
(3)??????,????????if????assign???? ????????????
54
??1?????????? comp.tf timescale 1ns/1ns module
t parameter n4 reg n-10 a,b wire
eq,ge,le integer i,j comp m
(.a(a),.b(b),.eq(eq),.ge(ge),.le(le)) //
Enter fixture code here initial
begin for(i0ilt16ii1) begin ai for(j0
jlt16jj1) begin bj 100 end end
end endmodule // t
(1)initial????? integer???? i ?j???? for?????????
i??????????
55
2.case??????????? ??2 ???? decoder.v module
decoder(enb,adr,y) input enb input 20
adr output 70 y reg 70 y always _at_(enb or
adr) begin if(!enb) case(adr)
3'b000 y8'b11111110 3'b001
y8'b11111101 3'b010
y8'b11111011 3'b011
y8'b11110111 3'b100
y8'b11101111 3'b101
y8'b11011111 3'b110
y8'b10111111 3'b111
y8'b01111111 endcase else
y8'b11111111 end endmodule
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(1)?????,if??????????????, case??????????????
case(???) ???1?1 ???2?2
default?n endcase ??????endcase??????
??????? (2)??????????, ( 2??)3'b001,8'b1111_110
1,8'bZZZZ_ZZZZ (16??)3'h1,8'hfc,8'hZZ????
'??????????? (3)if????(!enb)?,??(enb)?????????,
(!enb)?????? (4)else y8'b11111111
??????????????????
57
initial begin enb0 for(i0ilt8ii1)
begin adri 100 end enb1 for(i0ilt
8ii1) begin adri 100 end end endmodul
e // t
??2?????????? decoder.tf timescale
1ns/1ns module t reg enb reg 20 adr wire
70 y integer i decoder m
(.enb(enb),.adr(adr),.y(y)) // Enter fixture
code here
58
3.??????????? ??3 ??? adder.v module
adder(cin,a,b,cout,s) parameter n4 input
cin input n-10a,b output
n-10s output cout // assign
cout,sabcin reg n-10s reg cout alway
s_at_(a or b or cin) begin cout,sabcin end e
ndmodule
4
adder
4
a
s
4
b
cin
cout
(1)???,???,????????????????-??????
(2)??????,??????????????,????? , ????
cout,sabcin ?????????????
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??3?????????? adder.tf timescale 1ns/1ns module
t parameter n4 reg cin reg n-10a,b wire
n-10s wire cout integer i adder m
(.cin(cin),.a(a),.b(b),.cout(cout),.s(s)) //
Enter fixture code here
initial begin cin0 for(i0ilt256ii1)
begin a,bi 100 end cin1 for(i0i
lt256ii1) begin a,bi 100 end end end
module // t
???????????????????????????????????????????
60
4.??????????? ??4 ???????? dff.v module
dff(d,clk,sclr,aclr,enb,q,qsc,qac,qen) input
d,clk,sclr,aclr,enb output q,qsc,qac,qen reg
q,qsc,qac,qen // simple ff // always_at_(posedge
clk) q lt d // sync clear ff // always_at_(posedge
clk) if(sclr) qsc lt 0 else qsc lt d //
async clear ff // always_at_(posedge clk or negedge
aclr) if(aclr) qac lt 0 else qac lt d //
enb ff // always_at_(posedge clk) if(enb) qen lt
d endmodule
61
(1)????????????? always_at_(posedge clk)
????clk????????????always????????
????????FF??negedge?????? (2)????????,always_at_(??
?)? ?????????????????? (3)?????????,????????
????????? aclr???????posedge??????
(4)??????????????????? (5)?????????lt?????????
???????, ??????,???????????
????????????????????? ??,?????????????????????
?
62
??4?????????? dff.tf module t reg
d,clk,sclr,aclr,enb wire q,qsc,qac,qen dff
m (.d(d),.clk(clk), .sclr(sclr),.aclr(aclr),.enb(
enb), .q(q),.qsc(qsc),.qac(qac),.qen(qen))
// Enter fixture code here initial
begin clk0 forever begin 50
clkclk end end
initial begin aclr1 sclr1 enb1
d1 125 d0 200 d1 300
aclr0sclr0enb0 200 d0 300
aclr1sclr1enb1 200 d1 end endmodule
// t ???????????????forever ??????????
63
5.????????????????????? ??5 ????? edg.v module
edg(clk,d,reset,rise,fall) input
clk,d,reset output rise,fall reg
q1,q2 always_at_(posedge clk) begin if(!reset)
begin q10 end else begin q1d
end end always_at_(posedge clk)
begin if(!reset) begin q20 end else
begin q2q1 end end assign rise q1
!q2 assign fall!q1 q2 endmodule
rise
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(1)??????????,1???????????????, ??????????,???????
????????, ??????????????????? (2)??rise,fall????
?1??always???????????, lt ????????
?????? ????????????????????????????? lt????????
??,q1?q2??????,rise,fall????? always_at_(posedge
clk) begin if(!reset) begin q1lt0 q2lt0
end else begin q1ltd q2ltq1
end end (3)????????lt??????????????????? ???????
??????????????????????? (4)?????????????????????
?????? ?????????????????????????????
65
??5?????????? edg.tf timescale 1ns/1ns module
t reg clk,d,reset wire rise,fall edg m
(.clk(clk),.d(d),.reset(reset), .rise(rise),.fal
l(fall)) // Enter fixture code here initial
begin clk0 forever begin 50
clkclk end end
initial begin reset0 d0 75
reset1 200 d1 300 d0 400
d1 400 d0 end endmodule // t
66
6.??????????? ??6 countsc.v module
countsc(clk,clr,count) input clk,clr output
30count reg 30count always_at_(posedge
clk) begin if(!clr) count lt 0 else count
ltcount1 end endmodule
countsc
(1)???????????,?????FF???????????,
???????????,?????????? ?????????????????????????
???? (????)???10????????????????????
67
??6?????????? countsc.tf timescale
1ns/1ns module t reg clk,clr wire 30count
countsc m (.clk(clk),.clr(clr),.count(count))
// Enter fixture code here initial
begin clk0 forever begin 50
clkclk end end
initial begin clr1 125 clr0 200
clr1 end endmodule // t
68
countac
7.???????????? ??7 countac.v module
countac(clk,clr,count) input clk,clr output
30count reg 30count always_at_(posedge
clk or negedge clr) begin if(!clr) count lt
0 else count ltcount1 end endmodule
(1)????????????,??????FF???????
????,???????????,?????????? ???????????????????
?????????? (????)??????????????????????????
69
??7?????????? countac.tf timescale
1ns/1ns module t reg clk,clr wire 30count
countac m (.clk(clk),.clr(clr),.count(count))
// Enter fixture code here initial
begin clk0 forever begin 50
clkclk end end
initial begin clr1 125 clr0 200
clr1 end endmodule // t
70
8.?????????? ??8 state.v module
state(clk,a,res,ss) input clk,a,res output
10ss reg 10ss parameter
s002'b00 parameter s012'b01 parameter
s102'b10 parameter s112'b11 always_at_(posedge
clk) begin if(res) sss00 else
case(ss) s00 if(a) sss01 else
sss10 s01 if(a) sss11 s10 if(a)
sss11 s11 sss00 endcase end endmodule
1
S11
a
a
a
a
S01
S10
a
a
S00
71
(1)verilog????????????,??????
???????,parameter????,????????????? (2)??????????
,s00??????, ?? a1?? s00 ? s01 ? s11
(??,s01?a0??,s01???)
?
----- ?? a0?? s00 ? s10 ? s11 (??
,s10?a1??,s10???)
?
----- ????????case?????,???????????????
(3)?????????????? ????????????????? ??????????
????????? ????????????????????
72
??8?????????? state.tf timescale 1ns/1ns module
t reg clk,a,res wire 10ss state m
(.clk(clk),.a(a),.res(res),.ss(ss)) // Enter
fixture code here initial begin clk0 foreve
r begin 50 clkclk end end
initial begin res0a0 100
res1 700 res0a1 100
res1 end endmodule // t
73
9.????????? ??9 triout.v module
triout(a,oe,y) input a,oe output y assign
yoe? a 1'bZ endmodule
oe
a
y
(1)???????????????????????LSI? ??????????????
(2)1??????????????1'bZ???? Z??????????????????
8???? 8'bZZZZ_ZZZZ ??? 8'hZZ (3)??????????,?????
????assign??????? ??????????output????? (???)if
???????????????????????
74
??9?????????? triout.tf timescale 1ns/1ns module
t reg a,oe wire y integer i triout m
(.a(a),.oe(oe),.y(y)) // Enter fixture code
here initial begin oe0 450 oe1
500 end
initial begin a0 for(i0ilt10ii1)
100 aa end endmodule // t
75
10.???????? ??10 bidir.v module bidir(rd,wr,db)
input rd,wr inout db wire idb reg odb
assign idbdb always_at_(posedge
wr) odbltidb assign dbrd? 1'bZ
odb endmodule
D Q
(1)??????,?????????assign???????
??????inout????? (2)if??????????????????????????
?
76
??10?????????? bidir.tf timescale
1ns/1ns module t reg rd,wr wire db reg
rd_data bidir m (.rd(rd),.wr(wr),.db(db))
// Enter fixture code here task wr_task
input wr_dt begin force dbwr_dt 50
wr0 50 wr1 50 release db 50
end endtask
task rd_task output rd_dt
begin rd0 100 rd_dtdb rd1 100
end endtask initial begin rd1 wr1
db1'bZ 100 wr_task(1) rd_task(rd_data)
display("time4d rd_datab", time,rd_data)
100 wr_task(0) rd_task(rd_data)
display("time4d rd_datab", time,rd_data)
end endmodule // t
77
(1)?????????????????????????? (2)?????????task???
??endtask????? (3)?????task????????????
??????? wr_task ? rd_task ?????? (4)?????????????
?? wr_task???????wr_dt rd_task???????rd_dt ????
????? (5)?????initial????????????
wr_task?rd_task?2????????? ???????1?0????????????
?????
78
(6)?????db?????????????????????? (7)?????db????Z
????(Z?????) (8)?????db?Z?????????????force?????
(9)?????????????release????? (10)display?output
??????????????? ??????????????C???printf?????
time???????????????
79
Verilog????? ? ? ???????????????
80
1.??????????? ?????????????????????
(??1) 100Hz??????????????????4????? ?????Verilog-H
DL???????? start??????????????? stop????????????
??? ????????????? (??2) start???????????????????
??????? ??????????
81
?module digit(clk,res,cin,cout,led) input
clk,res,cin output cout output 60led
reg 30dgt reg 60led ?always_at_(
clk) begin if( ) dgtlt0 else if(cin
( )) dgtltdgt1 else if(cin
(dgt9)) dgtlt0 end ?assign coutcin (
) ?always_at_(dgt) begin case(dgt) 0 le
d7'h3f 1 led7'h06 2 led
3 led 4 led
5 led 6 led
7 led 8 led
9 led default
led7h00 endcase end endmodule
??????digit?LED?????? ????????????????7?? ????????
?????????? ???????clk??????res??? ????????????4???
??? ????10?????????9??? 0????????????? ???????????
????????9????????????????????? ?7?????????????????
??????????????????????
82
?module watch1(start,stop,clk,led1,led2,led3,led4)
input start,stop,clk output
60led1,led2,led3,led4 reg 10state
wire dres,enb1,enb2,enb3,enb4 ?parameter
reset2'b00 parameter count2'b01 parameter
display2'b10 ?always_at_(posedge clk)
begin if(start stop) statereset else
if( ) statecount else if( )
statedisplay end assign enb1( )
assign dres(statereset) ?digit
digit1(clk,dres,enb1,enb2,led1) ?digit
digit2(clk,dres, , ,led2) digit
digit3(clk,dres, , ,led3) digit
digit4(clk,dres, , ,led4) endmodule
??????watch1?????????? reset,count,display?3??????
??? ??????????????????? start???count? stop???di
splay? ???reset? ?digit1digit4????? digit1
1/100??? digit2 1/10??? digit3 1???
digit4 10??? ??????????????????? ?enb1enb4?
digit1digit4?????? ????????????????????
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2.??IO??? ?????8???3??????LSI (????8255????)????
???? cs rd wr adr ? ? H ? ? ?
00 DB?PA?? L L H 01 DB?PB?? 10
DB?PC?? 11 DB?CR???? 00
DB?PA???? L H ? 01 DB?PB???? 10
DB?PC???? 11 DB?CR???? CR?????PA?PB?PC??
??? ?????????? CR(0) 0 PA????? 1
PA????? CR(1) 0 PB????? 1 PB?????
CR(2) 0 PC????? 1 PC?????
PIO ADR PA CS PB RD WR PC DB
CR RES
8
2
8
8
8
RES?PA,PB,PC??? ???????????? ??????????
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??IO pio.v module pio(cs,rd,wr,adr,res,db,pa,pb,p
c) parameter n8 input cs,rd,wr,res input
10adr inout n-10db,pa,pb,pc reg
n-10qa,qb,qc,cr,odb / internal register
(reset , cs wr) / always_at_( or
) begin if( )begin qa0 qb0 qc0
cr8'hFF end else if( ) case(
) 0qadb 1qbdb 2qcdb 3crdb
endcase end
?
?qa,qb,qc,cr?wr?????? res????????????FF? cs??????
???db???adr? ?????qa,qb,qc,cr????? ????????
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/ port tri-state assign / assign pa(
)?qa8'hZZ assign pb(
)?qb8'hZZ assign pc( )?qc8'hZZ /
data selecter / always_at_( or or or
or ) begin case(adr) 0odbpa 1odbpb
2odbpc 3odbcr endcase end / databus
tri-state assign (cs rd) / assign db(
)? odb8'hZZ endmodule
?
?pa?cr0??????????????? pb?cr1???????????
???? pc?cr2???????????????
??pa,pb,pc,cr?????? adr??????? odb?????????
???????
?
?
?db?cs?rd????? ??????????????
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PIO?????????? pio.tf timescale 1ns/1ns module
t reg cs,rd,wr,res reg 10adr wire
70db,pa,pb,pc integer i reg
70rd_data pio m (.cs(cs),.rd(rd),.wr(wr),.ad
r(adr),.res(res),.db(db),.pa(pa),.pb(pb),.pc(pc))
assign papb // connect PB to PA //
Enter fixture code here task wr_task input
10adr_dt input 70wr_dt begin cs0
adradr_dt force dbwr_dt 50 wr0 100
wr1 50 cs1 adr2'b11 release
db 50 end endtask
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task rd_task input 10adr_dt output
70rd_dt begin cs0 adradr_dt
50 rd0 100 rd_dtdb
rd1 50 cs1 adr2'b11
50 end endtask initial begin cs1 rd1
wr1 adr2'b11 db8'bZZ res0 50 res1
50 wr_task(3,1) //write CW to CR (PAin
PB,PCout) for(i0ilt255ii1)
begin wr_task(1,i) // write to PB
rd_task(0,rd_data) // read from
PA display("ix rd_datax",i,rd_data) end
1000 finish end endmodule // t
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?module digit(clk,res,cin,cout,led) input
clk,res,cin output cout output 60led
reg 30dgt reg 60led ?always_at_(posedge
clk) begin if(res) dgtlt0 else if(cin
(dgt!9)) dgtltdgt1 else if(cin (dgt9))
dgtlt0 end ?assign coutcin
(dgt9) ?always_at_(dgt) begin case(dgt) 0 led
7'h3f 1 led7'h06 2 led
7h5b 3 led7h4f 4 led
7h66 5 led7h6d 6 led7h7d 7 led
7h27 8 led7h7f 9 led7h6f default
led7h00 endcase end endmodule
??? watch1.v
90
?module watch1(start,stop,clk,led1,led2,led3,led4)
input start,stop,clk output
60led1,led2,led3,led4 reg 10state
wire dres,enb1,enb2,enb3,enb4 ?parameter
reset2'b00 parameter count2'b01 parameter
display2'b10 ?always_at_(posedge clk)
begin if(start stop) statereset else
if(start stop) statecount else if(start
stop) statedisplay end assign
enb1(statecount) assign dres(statereset)
?digit digit1(clk,dres,enb1,enb2,led1) ?digit
digit2(clk,dres,enb2,enb3,led2) digit
digit3(clk,dres,enb3,enb4,led3) digit
digit4(clk,dres,enb4, ,led4) endmodule
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??? pio.v module pio(cs,rd,wr,adr,res,db,pa,pb,pc
) parameter n8 input cs,rd,wr,res input
10adr inout n-10db,pa,pb,pc reg
n-10qa,qb,qc,cr,odb / internal register
(reset , cs wr) / always_at_(posedge wr or
negedge res) begin if(res)begin qa0 qb0
qc0 cr8'hFF end else if(cs)
case(adr) 0qadb 1qbdb 2qcdb
3crdb endcase end
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/ port tri-state assign / assign
pa(cr0)?qa8'hZZ assign pb(cr1)?qb8'hZZ
assign pc(cr2)?qc8'hZZ / data
selecter / always_at_(adr or pa or pb or pc or
cr) begin case(adr) 0odbpa 1odbpb
2odbpc 3odbcr endcase end / databus
tri-state assign (cs rd) / assign db(cs
rd)? odb8'hZZ endmodule