Introduction to Verilog HDL.

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Introduction to Verilog HDL

• CEC

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Contents

• VLSI Design Flow.
• Design Methodologies.
• Examples.
• Module.
• Levels of Abstraction.
• Instantiation.
• Value Set, Nets, Registers and Vectors.

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VLSI Design Flow

• Steps for designing and constructing an
  Integrated Circuit Chip (IC).

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VLSI Design Flow
HDL
CAD Tools
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VLSI Design Flow

• Specifications describe the functionality,
  interface and overall architecture of the
  circuit.
• Behavioural description analyzes the design in
  terms of its functionality, performance and
  compliance to the standards and other high level
  issues, written with HDLs.

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VLSI Design Flow

• Behavioural description converted to Register
  Transfer Level (RTL) description.
• Designer to describe data flow for the circuit.
• Further design process using CAD/EDA tools after
  RTL is frozen.
• CAD Tools susceptible to Garbage In Garbage Out
  (GIGO).

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VLSI Design Flow

• Logic synthesis tools to convert RTL description
  to a gate-level netlist.
• Gate-level netlist describes the circuit in terms
  of gates and connections.
• Gate-level netlist as an input to Automatic Place
  and Route Tool (APR).
• APR creates the layout.
• Layout verified and fabricated on a chip.

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Garbage In Garbage Out

• CAD/EDA Tools to cut design cycle times.
• CAD/EDA Tools for optimizing the design.
• Designer controls tool performance.

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Design Methodologies

• Top-Down Design.
• Bottom-Up Design.
• Combination of both used.
• Design architects define specifications.
• Logic designers decide the structure.
• Circuit designers optimize circuits for leaf
  level cells, build higher level cells.

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Top-Down Design
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Bottom-Up Design
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Design Illustration Top Level Block
Circuit of a Ripple
Carry Counter
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Illustration Sub Block/ Leaf Cell
NOT Gate
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Design Hierarchy
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Counter Design Hierarchy

• Top Down Design Methodology
• - Break bigger blocks till we cannot break.
• - Specify the functionality of ripple carry
• counter top level block.
• - Implement counter with T- flipflops.
• - Build T- flipflops from D- flip flop and an
  
• inverter.

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Counter Design Hierarchy

• Bottom Up Design Methodology
• - Combine smaller building blocks to
• bigger blocks.
• - Start with D flipflop, build T flipflop,
  build
• counter using T-flipflops.

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Building blocks inVerilog

• Module
• Basic building block in Verilog.
• Module can be an element or a
• collection of lower level building
• blocks.
• Elements grouped into modules to
• provide common functionality.

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Module

• Provides necessary functionality to the higher
  level block through port interface (inputs and
  outputs).
• Allows designer to modify module internals
  without affecting rest of the design.
• Declared by the key word module and endmodule
  for the end of module

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Module

• Module name as identifier.
• Module terminal list describes I/O terminals of
  the module followed by internals and endmodule.

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T- flipflop defined as module
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Levels of Abstraction

• Behavioural or algorithmic level
• - Highest level of abstraction.
• - No concern for hardware details.
• - Similar to C programming.
• Data flow level
• - Module designed by specifying data flow.
• - How data flows and is processed.

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Levels of Abstraction

• Gate level
• - Module implemented in terms of logic
• gates and interconnections.
• Switch Level
• - Lowest level of abstraction.
• - Implemented in terms of switches,
• storage nodes and interconnections.
• Mix and match four levels of abstraction.

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Instantiation

• Objects called instances.
• Process of creating objects from a module
  template.
• Each instance given a unique name.
• Eg Each T- flipflop instantiates a D- flipflop
  and an inverter.

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Modules cannot be nested.
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Stimulus Block

• Also called test bench.
• Functionality of Design Block to be tested by
  applying stimulus.
• Stimulus block written in Verilog.
• Separate stimulus and design blocks.
• Interacts with design block through interface.

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Top Level Dummy Module
Instantiate Both
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Output
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Waveforms
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Comments

• Enhances readability, understandability and
  documentation.
• Single line comments start with //
• Multiple comments start with / and end with /.

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Value Sets
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Nets

• Connection between hardware elements.
• Declared using key word wire.

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Registers

• Storage element.
• A variable that can hold a value.
• Stores until rewritten.

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Vectors

• nets or reg datatypes can be declared as vectors.
• Default 1 bit.
• Can be declared as high low or low
  high

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Vectors
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Value Change Dump File
Simulation time, scope, signal definitions and
signal value changes
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An Online Verilog Simulator
Code Your Stimulus Block here
Code your Design Block here
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An Online Verilog Compiler
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Some Online Verilog Simulator Links

• http//www.techep.csi.cuny.edu/zhangs/v.html
• https//www.jdoodle.com/execute-verilog-online/

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Reference Book

• Samir Palnitkar, Verilog HDL, A Guide to Digital
  Design and Synthesis, SunSoft Press, 1996.

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Thank You