CS 230: Computer Organization and Assembly Language

1
CS 230 Computer Organization and Assembly
Language

• Aviral Shrivastava

Department of Computer Science and
Engineering School of Computing and
Informatics Arizona State University
Slides courtesy Prof. Yann Hang Lee, ASU, Prof.
Mary Jane Irwin, PSU, Ande Carle, UCB
2
Announcements

• Project 3
• Due October 19, 2009
• Midterm
• Thursday, October 22, 2009
• Contents
• MIPS ISA and Programming
• Function calls and register conventions
• Assembling MIPS Instructions
• 2s complement number system
• FP number system
• Finals
• Tuesday, Dec 08, 2009

3
Computer Organization
software
Instruction Set Architecture
hardware

• We have leaned the ISA of the processor till now
• Given an algorithm, express it in terms of the
  processor ISA

4
Below the Program

• High-level language program (in C)
• swap (int v, int k)
• . . .
• Assembly language program (for MIPS)
• swap sll 2, 5, 2
• add 2, 4, 2
• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)
• jr 31
• Machine (object) code (for MIPS)
• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000

C - Compiler
Assembler
5
Working of Computer
Processor
Devices
Control
Input
Memory
Datapath
Output
6
Input Device Inputs Object Code

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Processor
Devices
Control
Input
Memory
Datapath
Output
7
Object Code Stored in Memory
Memory
Processor
Devices

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Control
Input
Datapath
Output
8
Processor Fetches an Instruction
Processor fetches an instruction from memory
Memory
Processor
Devices

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Control
Input
Datapath
Output
9
Control Decodes the Instruction
Control decodes the instruction to determine what
to execute
Processor
Devices
Control
000000 00100 00010 0001000000100000
Memory
Input
Datapath
Output
10
Datapath Executes the Instruction
Datapath executes the instruction as directed by
control
Processor
Devices
Control
000000 00100 00010 0001000000100000
Memory
Input
Datapath
contents Reg 4 ADD contents Reg 2 results put
in Reg 2
Output
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Update the PC, and continue
Memory
Processor
Devices

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Control
Input
Datapath
Output
Fetch
Decode
Execute
12
Output Data Stored in Memory
At program completion the data to be output
resides in memory
Memory
Processor
Devices
Control
Input

• 00000100010100000000000000000000
• 00000000010011110000000000000100
• 00000011111000000000000000001000

Datapath
Output
13
Output Device Outputs Data
Processor
Devices
Control
Input
Memory
Datapath
Output

• 00000100010100000000000000000000
• 00000000010011110000000000000100
• 00000011111000000000000000001000

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MIPS ISA to Implement

• Arithmetic Instructions
• Add, sub, AND, OR, and slt (R-type)
• Memory access instructions
• LW, and SW (I-type)
• Branch instructions
• Beq (I-type)
• Jump instructions
• J (J-type)

15
MIPS Machine
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
16
Build a MIPS Processor

• Today Build the ALU
• Support all the Arithmetic/Logic operations

ALU control lines
ALU Control Lines Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 Set on less than
1100 NOR
a
ALU
32
result
b
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ALUOp and ALU control bits
Instruction Opcode ALUOp Instruction operation Funct field Desired ALU action ALU control input
LW 00 Load word XXXXXX add 0010
SW 00 Store word XXXXXX Add 0010
Beq 01 Branch equal XXXXXX Subtract 0110
R-type 10 Add 100000 Add 0010
R-type 10 Subtract 100010 Subtract 0110
R-type 10 AND 100100 AND 0000
R-type 10 OR 100101 OR 0001
R-type 10 Set on less than 101010 Set on less than 0111
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Implementation
Truth table for 4 ALU control bits
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Building a 1-bit Binary Adder
carry_in
A B carry_in carry_out S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
1 bit Full Adder
S
B
carry_out

• S A xor B xor carry_in
• carry_out (A and B) or (A and carry_in)
  or (B and carry_in)

• How can we use it to build a 32-bit adder?
• How can we modify it easily to build an
  adder/subtractor?

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Building 32-bit Adder

• Just connect the carry-out of the least
  significant bit FA to the carry-in of the next
  least significant bit and connect . . .
• Ripple Carry Adder (RCA)
• advantage simple logic, so small (low cost)
• disadvantage slow and lots of glitching (so
  lots of energy consumption)

21
Building 32-bit Adder/Subtractor

• Remember 2s complement is just
• complement all the bits
• add a 1 in the least significant bit

add/subt
B0
B1
B2
A 0111 ? 0111 B - 0110 ?  1010
B31
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Logic Operations

• Logic operations operate on individual bits of
  the operand.
• t2 00 0000 1101 0000
• t1 00 0011 1100 0000
• and t0, t1, t2 t0
• or t0, t1, t2 t0
• xor t0, t1, t2 t0
• nor t0, t1, t2 t0
• How do we expand our FA design to handle the
  logic operations - and, or, xor, nor ?

00 0000 1100 0000
00 0011 1101 0000
00 0011 0001 0000
11 1100 0010 1111
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A Simple ALU Cell
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Tailoring the ALU to the MIPS ISA

• Need to support the set-on-less-than instruction
  (slt)
• remember slt is an arithmetic instruction
• produces a 1 if rs lt rt and 0 otherwise
• use subtraction (a - b) lt 0 implies a lt b
• Need to support test for equality (beq)
• use subtraction (a - b) 0 implies a b
• Need to add the overflow detection hardware

25
Modifying the ALU Cell for slt
carry_in
add/subt
op
A
result
1-bit FA
B
carry_out
add/subt
26
ALU for slt

• First perform a subtraction
• Make the result 1 if the subtraction yields a
  negative result
• Make the result 0 if the subtraction yields a
  positive result

• tie the most significant sum bit (sign bit) to
  the low order less input

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ALU for Zero
op
add/subt
A0
result0

• First perform subtraction
• Insert additional logic to detect when all
  result bits are zero

B0

less
A1
result1
B1

0
less
. . .
A31

• Note zero is a 1 when result is all zeros

result31
B31

0
less
set
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Overflow Detection

• Overflow the result is too large to represent
  in the number of bits allocated
• On your own Prove you can detect overflow by
• Carry into MSB xor Carry out of MSB

1
1
6
7
29
Modifying the ALU for Overflow
op
add/subt
A0
result0

• Modify the most significant cell to determine
  overflow output setting
• Disable overflow bit setting for unsigned
  arithmetic

B0

less
A1
result1
B1
zero

. . .
0
less
. . .
A31
result31

B31
0
less
set
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Shift Operations

• Also need operations to pack and unpack 8-bit
  characters into 32-bit words
• Shifts move all the bits in a word left or right
• sll t2, s0, 8 t2 s0 ltlt 8 bits
• srl t2, s0, 8 t2 s0 gtgt 8 bits
• Such shifts are logical because they fill with
  zeros

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Shift Operations

• An arithmetic shift (sra) maintain the arithmetic
  correctness of the shifted value (i.e., a number
  shifted right one bit should be ½ of its original
  value a number shifted left should be 2 times
  its original value)
• so sra uses the most significant bit (sign bit)
  as the bit shifted in
• note that there is no need for a sla when using
  twos complement number representation
• sra t2, s0, 8 t2 s0 gtgt 8 bits
• The shift operation is implemented by hardware
  (usually a barrel shifter) outside the ALU

32
MIPS Machine
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
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Yoda says

• Use your feelings, Obi-Wan, and find him you will