CS 230: Computer Organization and Assembly Language

1
CS 230 Computer Organization and Assembly
Language

• Aviral Shrivastava

Department of Computer Science and
Engineering School of Computing and
Informatics Arizona State University
Slides courtesy Prof. Yann Hang Lee, ASU, Prof.
Mary Jane Irwin, PSU, Ande Carle, UCB
2
Announcements

• Important announcements will be made at the
  beginning of the lecture
• Blackboard is setup
• If you cannot access, let me know immediately
• Make it an interactive forum
• Lectures
• Will be fast paced, so read before and after the
  class
• Stop me as soon as you have a question, or you do
  not understand.
• Realize that it is your last chance
• Learning is your prerogative
• I will skip some things that are in the textbook,
  and will teach somethings that are not in the
  textbook
• Now you are in college

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More Announcements

• Green card in front of the book
• Take out half an hour to browse through it
• MARS MIPS Simulator
• Write programs in MIPS assembly language
• Is needed for projects 1 and 2
• Start playing with MARS
• Quiz will be 45 mins
• open book and notes
• One question will be difficult
• Quiz 1
• Thursday Sept 10, 2009.
• Arithmetic, Load/Store and Branch Instructions

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The Instruction Set Architecture (ISA)
software
instruction set architecture
hardware
ISA - The interface description separating the
software and hardware.
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Below the Program

• High-level language program (in C)
• swap (int v, int k)
• . . .
• Assembly language program (for MIPS)
• swap sll 2, 5, 2
• add 2, 4, 2
• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)
• jr 31
• Machine (object) code (for MIPS)
• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000

C - Compiler
Assembler
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Higher-Level Languages

• Higher-level languages
• Allow the programmer to think in a more natural
  language
• Customized for their intended use, e.g.,
• Fortran for scientific computation
• Cobol for business programming
• Lisp for symbol manipulation
• Improve programmer productivity and
  maintainability
• more understandable code that is easier to debug
  and validate
• Independent of
• Computer on which it applications are developed
• Computer on which it applications will execute
• Enabler
• Optimizing Compiler Technology
• Very little programming at the assembler level

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MIPS R3000 Instruction Set Architecture
Registers

• Instruction Categories
• Arithmetic
• Load/Store
• Jump and Branch
• Floating Point
• coprocessor
• Memory Management
• Special

R0 - R31
PC
HI
LO
3 Instruction Formats all 32 bits wide
rs
rt
OP
rd
sa
funct
rs
OP
rt
immediate
jump target
OP
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RISC Vs. CISC

• MIPS ISA is a RISC ISA
• RISC Reduced Instruction Set Computer
• CISC Complex Instruction Set Computer
• Many differences
• Will learn over the lectures
• One main difference
• In MIPS (a RISC architecture), all instructions
  are 32-bits
• In IA32 (a CISC architecture), instructions can
  be of variable widths

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MIPS ISA Arithmetic Instructions

• MIPS assembly language arithmetic statement
• add t0, s1, s2
• sub t0, s1, s2
• Each arithmetic instruction performs only one
  operation
• Each arithmetic instruction specifies exactly
  three operands
• destination ? source1 op source2
• All operands are contained in the Register File
• t0, s1,s2 are in Register File
• Operand order is fixed

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Compiling More Complex Statements

• What is the assembler equivalent of
• h (b - c) d
• Assume
• Variable b is stored in register s1
• Variable c is stored in s2
• Variable d is stored in s3
• Result is to be left in s0

sub t0, s1, s2 add s0, t0, s3
t0 b - c s0 t0 d
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MIPS Register File

• All source operands of arithmetic instructions
  must be from the Register File
• All the destination operands of arithmetic
  instructions must be written into the Register
  File
• Register File
• Holds thirty-two 32-bit registers
• Two read ports and
• One write port
• Registers are
• Faster than main memory
• Easier for a compiler to use
• e.g., (AB) (CD) (EF) can do multiplies in
  any order vs. stack
• Can hold variables so that
• code density improves (since register are named
  with fewer bits than a memory location)
• Register addresses are indicated by using

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Register Naming Convention
16 s0 callee saves . . . (caller can
clobber) 23 s7 24 t8 temporary
(contd) 25 t9 26 k0 reserved for OS
kernel 27 k1 28 gp pointer to global
area 29 sp stack pointer 30 fp frame
pointer 31 ra return address (Hardware)
0 zero constant 0 (Hardware) 1 at reserved for
assembler 2 v0 expression evaluation
3 v1 function results 4 a0 arguments 5 a1 6
a2 7 a3 8 t0 temporary caller saves . .
. (callee can clobber) 15 t7
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MIPS ALU
32-bit

• 32-bit ALU
• 2 32-bit sources
• 1 32-bit result
• Operations
• Arithmetic
• ADD, SUB, ...
• Logical
• AND, OR, NOR, XOR,

32-bit
ALU
32-bit
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How does it work?
Register File
R0
R1
src1 reg no
17
R8
src1 data
15
src2 reg no
25
R17
25
18
R18
10
src2 data
dst addr
8

• sub t0, s1, s2

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write data
15
R31
s1 ? R17
25
t0 ? R8
s2 ? R18
10
-

• Arithmetic instructions can only change the
  contents of the Register File
• In CISC processors, arithmetic instructions are
  much more powerful they can read and change the
  contents of the memory

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MIPS R3000 Instruction Set Architecture
Registers

• Instruction Categories
• Arithmetic
• Load/Store
• Jump and Branch
• Floating Point
• coprocessor
• Memory Management
• Special

R0 - R31
PC
HI
LO

• 3 Instruction Formats all 32 bits wide

rs
rt
OP
rd
sa
funct
rs
OP
rt
immediate
jump target
OP
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Memory

• Arithmetic instructions operands must be
  registers
• How do we get data into and out of memory?
• Remember, program and data reside in memory (Not
  in registers)
• What about programs with a lot of variables?

Processor
Devices
Control
Input
Memory
Datapath
Output
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Accessing Memory

• MIPS has two basic data transfer instructions for
  accessing memory
• lw t0, 4(s3) load word from memory
• sw t0, 8(s3) store word to memory
• 
  (assume s3 holds 2410)
• The data transfer instruction must specify
• Memory address
• where in memory to read from (load) or write to
  (store)
• Register destination (source)
• where in the register file to write to (load) or
  read from (store)
• The memory address is formed by
• summing the constant portion of the instruction
  and the contents of the second register

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32
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Processor Memory Interconnections

• Memory is viewed as a large, single-dimension
  array, with an address
• A memory address is an index into the array

read addr/ write addr
232
Processor
? locations
Memory
read data
write data
? width
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Memory Organization

• How wide is the memory
• What is each unit
• Each unit is a bit
• 0, 1
• 8-bits 1 byte
• In MIPS memory is byte addressable
• 232 locations of 1 byte
• Software likes to operate on words
• 1 word 4 bytes 32 bits
• 230 locations of 1 word

232 Locations
Memory
8-bit
230 Locations
Memory
32-bit
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MIPS Memory Addressing

• The memory address is formed by summing the
  constant portion of the instruction and the
  contents of the second (base) register
• lw t0, 4(s3) what? is loaded into t0
• sw t0, 8(s3) t0 is stored where?

. . . 0001
in location 16
24
. . . 0 1 1 0
Memory
s3 holds 8
20
. . . 0 1 0 1
16
. . . 1 1 0 0
. . . 0 0 0 1
12
. . . 0 0 0 1
. . . 0001
8
. . . 0 0 1 0
4
. . . 1 0 0 0
. . . 0 1 0 0
0
Data
Word Address
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Compiling with Loads and Stores

• Assume
• Variable b is stored in s2
• Base address of array A is in s3
• What is the MIPS assembly code for
• A8 A2 - b

. . .
. . .
s312
A3
lw t0, 8(s3) sub t0, t0, s2 sw t0, 32(s3)
s38
A2
s34
A1
s3
A0
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Compiling with a Variable Array Index

• Assume
• A is an array of 50 elements
• Base of A is in register s4
• Variables b, c, and i are in s1, s2, and s3
• What is the MIPS assembly code for
• c Ai - b

add t1, s3, s3 array index i is in
s3 add t1, t1, t1 temp reg t1 holds 4i
add t1, t1, s4 addr of Ai lw t0,
0(t1) sub s2, t0, s1
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Assembly Generation Arithmetic Instructions

• Instructions, like registers and words of data,
  are also 32 bits long
• Example add t0, s1, s2
• registers have numbers t08, s117, s218
• Instruction Format

op rs rt rd
shamt funct
000000 10001 10010 01000 00000
100000
What do the field names stand for?
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MIPS Instruction Fields
R Format
op rs rt rd
shamt funct
32 bits
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits

• op
• rs
• rt
• rd
• shamt
• funct

opcode indicating operation to be performed
address of the first register source operand
address of the second register source operand
the register destination address
shift amount (for shift instructions)
function code that selects the specific variant
of the operation specified in the opcode field
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Assembly Generation Load Instruction

• Consider the load-word and store-word
  instructions,
• What would the regularity principle have us do?
• New principle Good design demands a compromise
• Introduce a new type of instruction format
• I-type for data transfer instructions
• previous format was R-type for register
• Example lw t0, 24(s2)

I Format
op rs rt 16
bit number
35 18 8
24
100011 10010 01000
0000000000011000
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Assembly Generation Store Instruction

• sw t0, 24(s2)

op rs rt
16 bit number
43 18 8
24
101011 10010 01000 0000000000011000

• A 16-bit address means access is limited to
  memory locations within a region of ?213 or 8,192
  words (?215 or 32,768 bytes) of the address in
  the base register s2

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Assembling Code

• Example
• A8 A2 b
• lw t0, 8(s3) load A2 into t0
• sub t0, t0, s2 subtract b from A2
• sw t0, 32(s3) store result in A8
• Assemble the MIPS code for these three
  instructions

lw
35
19
8
8
0
sub
8
18
8
0
34
43
sw
19
8
32
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MIPS Data Types
Bit 0, 1 Bit String sequence of bits of a
particular length 4 bits is a nibble
8 bits is a byte 16 bits is a half-word
32 bits is a word 64 bits is a
double-word Character ASCII 7 bit
code Integers Unsigned Integers
Signed Integers - 2's complement Floating Point

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Decimal, Hexadecimal, and Binary
1010 1100 0011 (binary) 0xAC3 10111 (binary)
0001 0111 (binary) 0x17 0x3F9 11 1111 1001
(binary)
00 0 000001 1 000102 2 001003 3
001104 4 010005 5 010106 6 011007 7
011108 8 100009 9 100110 A 101011 B
101112 C 110013 D 110114 E 111015 F
1111
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Unsigned Binary Representation
Hex Binary Decimal
0x00000000 00000 0
0x00000001 00001 1
0x00000002 00010 2
0x00000003 00011 3
0x00000004 00100 4
0x00000005 00101 5
0x00000006 00110 6
0x00000007 00111 7
0x00000008 01000 8
0x00000009 01001 9

0xFFFFFFFC 11100 232-4
0xFFFFFFFD 11101 232-3
0xFFFFFFFE 11110 232-2
0xFFFFFFFF 11111 232-1
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Signed Binary Representation
2s C binary decimal
1000 -8
1001 -7
1010 -6
1011 -5
1100 -4
1101 -3
1110 -2
1111 -1
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
-23
-(23 - 1)
1011 and add a 1
1010 complement all the bits
23 - 1
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Memory Address Location
Memory

• lw t0, 24(s2)
• 2410 s2

0xf f f f f f f f
. . . 1001 0100 . . . 0001 1000 . . .
1010 1100 0x120040ac
0x00000002
s2
0x12004094
0x0000000c
Note that the offset can be positive or negative
0x00000008
0x00000004
0x00000000
data
word address (hex)
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MIPS Instructions, so far
Category Instr Op Code Example Meaning
Arithmetic (R format) add 0 and 32 add s1, s2, s3 s1 s2 s3
Arithmetic (R format) subtract 0 and 34 sub s1, s2, s3 s1 s2 - s3
Data transfer (I format) load word 35 lw s1, 100(s2) s1 Memory(s2100)
Data transfer (I format) store word 43 sw s1, 100(s2) Memory(s2100) s1
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Review MIPS R3000 ISA
Registers

• Instruction Categories
• Arithmetic
• Load/Store
• Jump and Branch
• Floating Point
• coprocessor
• Memory Management
• Special

R0 - R31
PC
HI
LO

• 3 Instruction Formats all 32 bits wide

6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
R Format
rs
rt
OP
rd
sa
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
I Format
rs
OP
rt
immediate
jump target
OP
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Review MIPS Organization so far

• Arithmetic instructions to/from the register
  file
• Load/store instructions - to/from memory

Memory
Processor
11100
Register File
read/write addr
src1 addr
src1 data
5
32
230 words
32
src2 addr
32 registers (zero - ra)
5
dst addr
read data
5
src2 data
write data
32
32
32
32 bits
write data
01100
32
32
01000
ALU
32
00100
7
6
5
4
32
00000
0
1
2
3
32 bits
word address (binary)
byte address (big Endian)
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Review Naming Convention for Registers
16 s0 callee saves . . . (caller can
clobber) 23 s7 24 t8 temporary
(contd) 25 t9 26 k0 reserved for OS
kernel 27 k1 28 gp pointer to global
area 29 sp stack pointer 30 fp frame
pointer 31 ra return address (Hardware)
0 zero constant 0 (Hardware) 1 at reserved for
assembler 2 v0 expression evaluation
3 v1 function results 4 a0 arguments 5 a1 6
a2 7 a3 8 t0 temporary caller saves . .
. (callee can clobber) 15 t7
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MIPS Data Types
Bit 0, 1 Bit String sequence of bits of a
particular length 4 bits is a nibble
8 bits is a byte 16 bits is a half-word
32 bits is a word 64 bits is a
double-word Character ASCII 7 bit
code Integers Unsigned Integers
Signed Integers - 2's complement Floating Point

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Yoda says

• Named must your fear be before banish it you can