CS 230: Computer Organization and Assembly Language

1
CS 230 Computer Organization and Assembly
Language

• Aviral Shrivastava

Department of Computer Science and
Engineering School of Computing and
Informatics Arizona State University
Slides courtesy Prof. Yann Hang Lee, ASU, Prof.
Mary Jane Irwin, PSU, Ande Carle, UCB
2
Announcements

• Project 3
• MIPS Assembler
• Midterm
• Thursday, Oct 2009
• MIPS ISA and Programming
• Function calls and register conventions
• Assembling MIPS Instructions
• 2s complement number system
• FP number system
• Finals
• Tuesday, Dec 08, 2009

3
Computer Organization
software
Instruction Set Architecture
hardware

• We have leaned the ISA of the processor till now
• Given an algorithm, express it in terms of the
  processor ISA

4
Below the Program

• High-level language program (in C)
• swap (int v, int k)
• . . .
• Assembly language program (for MIPS)
• swap sll 2, 5, 2
• add 2, 4, 2
• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)
• jr 31
• Machine (object) code (for MIPS)
• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000

C - Compiler
Assembler
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Datapath Control

• We're ready to look at an implementation of the
  MIPS
• Simplified to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq, j
• Generic implementation
• use the program counter (PC) to supply the
  instruction address and fetch the instruction
  from memory (and update the PC)
• decode the instruction (and read registers)
• execute the instruction
• All instructions (except j) use the ALU after
  reading the registers
• Why? memory-reference? arithmetic? control flow?

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Abstract Implementation View

• Two types of functional units
• elements that operate on data values
  (combinational)
• elements that contain state (sequential)
• Single cycle operation
• Split memory (Harvard) model - one memory for
  instructions and one for data

Write Data
Instruction Memory
Address
Read Data
Register File
Reg Addr
Data Memory
Read Data
Address
Instruction
ALU
PC
Reg Addr
Read Data
Write Data
Reg Addr
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32-bit ALU

• Supports all the Arithmetic/Logic operations

operation
a
ALU
32
result
b
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ALU Design
op
add/subt
A0
result0
B0

less
A1
result1
B1
zero

. . .
0
less
. . .
A31
result31

B31
0
less
set
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Fetching Instructions

• Fetching instructions involves
• reading the instruction from the Instruction
  Memory
• updating the PC to hold the address of the next
  instruction
• PC is updated every cycle, so it does not need an
  explicit write control signal
• Instruction Memory is read every cycle, so it
  doesnt need an explicit read control signal

Add
4
Instruction Memory
Read Address
Instruction
PC
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Decoding Instructions

• Decoding instructions involves
• sending the fetched instructions opcode and
  function field bits to the control unit

Control Unit
Instruction

• reading two values from the Register File
• Register File addresses are contained in the
  instruction

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Executing R Format Operations

• R format operations (add, sub, slt, and, or)
• perform the indicated (by op and funct) operation
  on values in rs and rt
• store the result back into the Register File
  (into location rd)
• Note that Register File is not written every
  cycle (e.g. sw), so we need an explicit write
  control signal for the Register File

ALU control
RegWrite
Read Addr 1
Read Data 1
Register File
Read Addr 2
overflow
Instruction
zero
ALU
Write Addr
Read Data 2
Write Data
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Load and Store Operations

• Load and store operations
• compute a memory address by adding the base
  register (in rs) to the 16-bit signed offset
  field in the instruction
• base register was read from the Register File
  during decode
• offset value in the low order 16 bits of the
  instruction must be sign extended to create a
  32-bit signed value
• store value, read from the Register File during
  decode, must be written to the Data Memory
• load value, read from the Data Memory, must be
  stored in the Register File

13
Load and Store Operations
14
Load and Store Operations
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Executing Branch Operations

• Branch operations have to
• compare the operands read from the Register File
  during decode (rs and rt values) for equality
  (zero ALU output)
• compute the branch target address by adding the
  updated PC to the sign extended16-bit signed
  offset field in the instruction
• base register is the updated PC
• offset value in the low order 16 bits of the
  instruction must be sign extended to create a
  32-bit signed value and then shifted left 2 bits
  to turn it into a word address

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Executing Branch Operations
Branch target address
Add
Add
4
Shift left 2
ALU control
PC
zero
(to branch control logic)
Read Addr 1
Read Data 1
Register File
Read Addr 2
Instruction
ALU
Write Addr
Read Data 2
Write Data
Sign Extend
16
32
17
Executing Branch Operations
Branch target address
Add
Add
4
Shift left 2
ALU control
PC
zero
(to branch control logic)
Read Addr 1
Read Data 1
Register File
Read Addr 2
Instruction
ALU
Write Addr
Read Data 2
Write Data
Sign Extend
16
32
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Executing Jump Operations

• Jump operations have to
• replace the lower 28 bits of the PC with the
  lower 26 bits of the fetched instruction shifted
  left by 2 bits

31
25
0
J-Type
jump target address
op
Add
4
4
Jump address
Instruction Memory
Shift left 2
28
Read Address
Instruction
PC
26
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Adding the pieces together
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Multiplexor Insertion
21
Clock Distribution
22
Adding the Branch Portion
23
Adding the Jump Portion
Jump
32
26
1
Shift left 2
28
PC431-28
0
Add
Add
4
Shift left 2
PCSrc
Instruction Memory
Read Address
Instruction
PC
24
MIPS Machine (with Controls)
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
25
Yoda says

• Use your feelings, Obi-Wan, and find him you will