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Verilog-HDL

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Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of s in this lecture are supported by Prof. – PowerPoint PPT presentation

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Title: Verilog-HDL


1
Verilog-HDL
Reference Verilog HDL a guide to digital design
and synthesis, Palnitkar, Samir Some of slides in
this lecture are supported by Prof. An-Yeu Wu,
E.E., NTU.
2
OUTLINE
  • Introduction
  • Basics of the Verilog Language
  • Gate-level modeling
  • Data-flow modeling
  • Behavioral modeling
  • Task and function

3
Verilog HDL (continue)
  • Invented by Philip Moorby in 1983/ 1984 at
    Gateway Design Automation ( Prabhu Goel,
    President )
  • Enables specification of a digital system at a
    range of levels of abstraction switches, gates,
    RTL, and higher
  • Initially developed in conjunction with the
    Verilog simulator

4
Verilog HDL
  • Verilog- based synthesis tool introduced by
    Synopsys in 1987
  • Gateway Design Automation bought by Cadence in
    1989
  • Verilog placed in public domain to compete with
    VHDL
  • Open Verilog International (OVI) IEEE 1364
    -1995 and
  • revised version IEEE 1364 -2001
  • revised version IEEE 1364 -2001

5
(No Transcript)
6
What is Verilog HDL ?
  • Mixed level modeling
  • Behavioral
  • Algorithmic ( like high level language)
  • Register transfer (Synthesizable)
  • Structural
  • Gate (AND, OR )
  • Switch (PMOS, NOMS, JFET )
  • Single language for design and simulation
  • Built-in primitives and logic functions
  • User-defined primitives
  • Built-in data types
  • High-level programming constructs

7
Basic Conventions
  • Verilog is case sensitive
  • Keywords are in lowercase
  • Extra white space is ignored
  • But whitespace does separate tokens
  • Comments
  • One liners are //
  • Multiple lines / /
  • Comments may not be nested

8
OUTLINE
  • Introduction
  • Basics of the Verilog Language
  • Overview of Verilog Module
  • Identifier Keywords
  • Logic Values
  • Data Types
  • Numbers Negative Numbers
  • Gate-level modeling
  • Data-flow modeling
  • Behavioral modeling
  • Task and function

9
Overview of Verilog Module
Test bench
10
Basic unit --Module
  • module module_name (port_name)
  • port declaration
  • data type declaration
  • module functionality or structure
  • Endmodule

11
D-FlipFlop
  • module D_FF(q,d,clk,reset)
  • output q //port declaration
  • input d,clk,reset // data type declaration
  • reg q
  • always _at_ (posedge reset or negedge clk)
  • if (reset)
  • q1'b0
  • else
  • qd
  • endmodule

12
Instance
  • A module provides a template which you can create
    actual objects.
  • When a module is invoked, Verilog creates a
    unique object from the template
  • The process of creating a object from module
    template is called instantiation
  • The object is called instance

13
Instances
  • module adder (in1,in2,cin,sum,cout)
  • .......
  • endmodule

module adder8(....) adder add1(a,b,1b0,s1,c1)
, add2(.in1(a2),.in2(b2),.cin(c1),.sum(s2)
,.cout(c2)) ..... endmodule
Mapping port positions
Mapping names
14
T-FlipFlop
  • module T_FF(q,clk,reset)
  • output q
  • input clk,reset
  • wire d
  • D_FF dff0(q,d,clk,reset) // create an instance
  • not n1(d,q)
  • endmodule

15
Identifier Keywords
  • Identifier
  • User-provided names for Verilog objects in the
    descriptions
  • Legal characters are a-z, A-Z, 0-9, _,
    and
  • First character has to be a letter or an _
  • Example Count, _R2D2, FIVE
  • Keywords
  • Predefined identifiers to define the language
    constructs
  • All keywords are defined in lower case
  • Cannot be used as identifiers
  • Exampleinitial, assign, module, always.
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