Tensilica Viterbi Implemenation

1
Tensilica Viterbi Implemenation

• Niraj Shah
• Scott Weber
• 290A Final Presentation

2
Tensilica Flow
3
Xtensa Architecture

• TIE Extensions
• single cycle
• state free
• no new exceptions
• no stalls
• typeless data
• Rs, Rt, Rr are 32 bit regs
• I is the instruction controlling the TIE unit
• Xtensa Core is a 32 bit configurable RISC
  processor

4
Viterbi Architecture
Measured Performance Here
5
TIE SetupBMreg (ACS)
6
ACS TIE Extension (ACS)
7
ACS TIE Extension with State (ACS)
8
TIE Zmask (TraceBack)
9
Designs

• All designs had a BER of 0.000095 after 10
  million iterations
• Design 1
• 100 MHz, 48 mW, 1K DCache, 1K ICache, TIE
• Design 1
• 222 MHz, 144 mW, 1K DCache, 1K ICache, TIE
• Design 2-
• 100 MHz, 69 mW, 16K DCache, 16K ICache, TIE
• Design 2
• 222 MHz, 191 mW, 16K DCache, 16K ICache, TIE
• Design 3
• 222 MHz, 191 mW, 16K DCAche, 16K ICache, TIE with
  state

10
Performance
Kb/s
11
Energy Dissipation
uJ/bit
12
n(sJ)/Bit
n(sJ)/ Bit
13
Die Area
mm2
14
Conclusions

• TIE extensions, cache configuration, and improved
  code efficiency resulted in an order of magnitude
  improvement from our original
• For power and performance, the effect of cache
  size is greater than the effect of a higher clock
  frequency
• If streaming date, then scale frequency
• Adding state will result in the ability to
  increase performance
• Having the ability to remove core instructions
  will decrease decode complexity and should lower
  power and area