Title: Viterbi Decoder: Presentation
1Viterbi Decoder Presentation 11
Overall Project Objective Design a high speed
Viterbi Decoder
Stage 11 12th April 2004 Short Final
Presentation
Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun
M1
- Design Manager Yaping Zhan
2Status
- Design Proposal (Done)
- Architecture Proposal (Done)
- Gate level Design (Done)
- Component Layout (Done)
- Component Simulation (Done)
- Chip Layout (Done)
- Spice simulation of entire chip (In progress)
18-525, Integrated Circuits Design Project
3Marketing
- What is a Viterbi Decoder?
- Uses and applications
- Example
- Why our design is useful?
- High speed
- Compact
3 Slides
18-525, Integrated Circuits Design Project
4Algorithm Description
- Brief overview
- How/Why it works
- Dataflow of our design
- Break down of each component
5 Slides
18-525, Integrated Circuits Design Project
5Implementation
- Overview
- Decision on design goal high speed
- Schematic
- Description
2 Slides
18-525, Integrated Circuits Design Project
6Verification
- Matlab Simulations
- Overview
- How/Why it works
- Verilog Simulations
- Overview
- How/Why it works
- Behavioral/Structural
- Top level schematic Simulation
- Overview
- How/Why it works
- Top level layout Simulation
- LVS
- Spice
15 Slides
18-525, Integrated Circuits Design Project
7Floorplan Evolution
- Floorplan ideas
- Overview
- Various implementations
- Initial floorplan
- Description
- Rejection
- Final floorplan
- Description
- Acceptance
8 Slides
18-525, Integrated Circuits Design Project
8Issues
- Floorplanning
- Wiring
- Wrong connections
- Decisions on top level routing
- Simulation
- Checking for critical path
- Space
- Gripe
1 Slide
18-525, Integrated Circuits Design Project
9Specifications
- Pin Specs
- Part Specs
- Evolution (Intial, changes, final)
- Chip Specs
- Evolution
3 Slides
18-525, Integrated Circuits Design Project
10Layout
- Masks
- Active
- Poly
- Metals 1, 2, 3, 4
- Full chip layout
- With overlaid floorplan
8 Slides
18-525, Integrated Circuits Design Project
11Conclusions
1 Slide
18-525, Integrated Circuits Design Project
12Emulations
- Matlab
- Verilog
- Schematic
- LVS
- Spice
5 Slides
18-525, Integrated Circuits Design Project
13Allocation of slides
- Marketing
- Algorithm Description
- Implementation
- Verification
- Floorplan Evolution
- Issues
- Specifications
- Layout
- Conclusions
- Emulations
Lingyan
Saim
Prateek
Omar
Total no. of slides 50
18-525, Integrated Circuits Design Project
14Updates
- We were running full chip simulation but
- Takes a long time
- People are very very very bad
- Added counter
- Provides robustness to design
- Extra part
18-525, Integrated Circuits Design Project
15Added Counter
16Final Dimensions
Total Area 309.96 um x 231.48 um 71,749.54 sq.
um Transistor Count 17,857 218
18,075 Transistor Density 0.252 Aspect Ratio
1.339 Estimated Clock Speed 300 MHz. Clock
Speed Achieved 500 MHz.
18-525, Integrated Circuits Design Project
17Questions/Comments
18-525, Integrated Circuits Design Project