Viterbi Decoder: Presentation

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Viterbi Decoder Presentation 11
Overall Project Objective Design a high speed
Viterbi Decoder
Stage 11 12th April 2004 Short Final
Presentation
Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun
M1

• Design Manager Yaping Zhan

2
Status

• Design Proposal (Done)
• Architecture Proposal (Done)
• Gate level Design (Done)
• Component Layout (Done)
• Component Simulation (Done)
• Chip Layout (Done)
• Spice simulation of entire chip (In progress)

18-525, Integrated Circuits Design Project
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Marketing

• What is a Viterbi Decoder?
• Uses and applications
• Example
• Why our design is useful?
• High speed
• Compact

3 Slides
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Algorithm Description

• Brief overview
• How/Why it works
• Dataflow of our design
• Break down of each component

5 Slides
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Implementation

• Overview
• Decision on design goal high speed
• Schematic
• Description

2 Slides
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Verification

• Matlab Simulations
• Overview
• How/Why it works
• Verilog Simulations
• Overview
• How/Why it works
• Behavioral/Structural
• Top level schematic Simulation
• Overview
• How/Why it works
• Top level layout Simulation
• LVS
• Spice

15 Slides
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Floorplan Evolution

• Floorplan ideas
• Overview
• Various implementations
• Initial floorplan
• Description
• Rejection
• Final floorplan
• Description
• Acceptance

8 Slides
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Issues

• Floorplanning
• Wiring
• Wrong connections
• Decisions on top level routing
• Simulation
• Checking for critical path
• Space
• Gripe

1 Slide
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Specifications

• Pin Specs
• Part Specs
• Evolution (Intial, changes, final)
• Chip Specs
• Evolution

3 Slides
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Layout

• Masks
• Active
• Poly
• Metals 1, 2, 3, 4
• Full chip layout
• With overlaid floorplan

8 Slides
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Conclusions
1 Slide
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Emulations

• Matlab
• Verilog
• Schematic
• LVS
• Spice

5 Slides
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Allocation of slides

• Marketing
• Algorithm Description
• Implementation
• Verification
• Floorplan Evolution
• Issues
• Specifications
• Layout
• Conclusions
• Emulations

Lingyan
Saim
Prateek
Omar
Total no. of slides 50
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Updates

• We were running full chip simulation but
• Takes a long time
• People are very very very bad
• Added counter
• Provides robustness to design
• Extra part

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Added Counter
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Final Dimensions
Total Area 309.96 um x 231.48 um 71,749.54 sq.
um Transistor Count 17,857 218
18,075 Transistor Density 0.252 Aspect Ratio
1.339 Estimated Clock Speed 300 MHz. Clock
Speed Achieved 500 MHz.
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Questions/Comments
18-525, Integrated Circuits Design Project