Viterbi Decoder: Presentation

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Viterbi Decoder Presentation 1
Overall Project Objective Design of a high speed
Viterbi Decoder
Stage 1 21 Jan. 2004 Project Proposal

• Omar Ahmad
• Prateek Goenka
• Saim Qidwai
• Lingyan Sun

M1
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Status

• Design Proposal (done)
• Architecture (in progress)
• To be done
• Floor Plan
• Gate Level Design
• Component Layout
• Chip Layout
• Spice Simulation of Entire Chip

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What is Viterbi Decoder?

• A processor that implements the Viterbi algorithm
  
• Widely used in digital communication and storage
• Cellular telephone convolutional code
  decoding
• Magnetic, optical disk drives channel
  detector

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Why Viterbi Decoder

• Example Hard disk drive

GOOD
01000111, 01001111, 01001111, 01000100
01010011, 01001100, 01001111, 01010111
SLOW

• Viterbi algorithm
• Take the received signal
• Find out the most likely input sequence

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The Viterbi Algorithm

• Calculation along the trellis

• Implementation Architecture

Branch Calculation Unit
Add Compare Select Unit
Maximum Likelihood Path Search
Trace FIFO
Trace Back Control Unit
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Schematic Diagram
C0
C1
C2
C3
Cn-1
Cn
Input

BCU
Control Logic
Input_valid

ACS
FIFO trace back
D

D
D

D

D
D
..
..
Vdd
D
D
D
D
Gnd
ML Search
Clock
Reset
Output
Output_valid
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Transistor Estimate
1000
Design Goal High speed
Above No. of components x No. of transistors
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Other Ideas

• Equalizer
• Fast Fourier Transform
• Adaptive Filter
• Auto-Regressive Filter

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Questions?