Implementing the Viterbi algorithm on programmable processors

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Implementing the Viterbi algorithm on
programmable processors

• Sridhar Rajagopal
• Elec 696
• sridhar_at_rice.edu

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Motivation

• Viterbi decoding - One of the major bottlenecks
  in baseband processing PHY
• Need for flexibility in the algorithm parameters
  due to different protocols read programmable
• No architecture developed yet to meet real-time
  requirements of 3G systems.
• 2 - 8 Mbps range for wideband CDMA
• 100 Mbps range for wireless LAN

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Today

• Background
• Advanced DSP architectures -- TI C6x 15
• Viterbi algorithm basics 10
• Viterbi on TI DSPs 10
• A programmable processor specifically designed
  for Viterbi 15

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TI C6x architecture

• VLIW Very Long Instruction Word arch.
• Similar to a vector processor -- but
• multiple instructions -gt multiple Func. Units
• FUs are not all the same
• 32-bit architecture
• 8 functional units

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8 VelociTI principles

• Parallel fetch, decode and execute
• Pipelined enough to make ADD critical path
• Instructions based on RISC
• Load - Store architecture
• Orthogonal - Instruction Set and Reg. File
• Determinism
• Conditional Instructions
• Instruction Packing

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2 4 8 Functional Units

• .M Multiplication unit
• 16 bit x 16 bit signed/ packed/
• .L arithmetic Logic unit
• Comparisons and logic operations
• Saturation arithmetic and absolute value
• .S Shifter unit
• Bit manipulation (set, get, shift, rotate)
• Branching, addition and packed addition
• .D Data unit
• Load/store to memory
• Addition and pointer arithmetic

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How powerful am I?

• 8 instructions per cycle
• Max
• 6 adds per cycle
• 2 multiplies per cycle
• 2 load/stores per cycle
• 2 branches per cycle
• Idea is you will be using instructions in these
  ratios to get full FU utilization.

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C6x DSP Core
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C6x Datapath
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C6x Resource Constraints

• Instructions using the same FU
• 1 inst. / FU
• Cross Paths
• only 1 operand from other reg. file to (L,S,M)
• Loads and stores
• 2 loads and stores from 2 different reg. files
• Reads and writes
• max 4-reads from the same register
• No 2 writes to the same register )

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Instruction Packing

• Fetch Packet
• Execute Packet
• Avoid NOPs in the instruction code
• Multi-cycle NOPs if absolutely necessary
• LSB- p bit of instruction for packing

A B C ,D E, F, G H 8 instructions
instead of 32
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Conditional Instructions

• All instructions can be conditioned based on the
  value in registers A1,A2,B0,B1,B2
• Avoids branch latencies
• If condition not met by end of first phase of
  execution, results not written back to reg. file
• Conditional loads/stores squashed before data
  phase

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C6x Pipeline

• Fetch (if necessary) - 4 phases
• Address Generate
• Address Send
• Access Ready Wait
• Fetch Packet Receive
• Decode - 2 phases
• Instruction dispatch (if necessary)
• Instruction decode
• Execute - 10 phases
• Most 1 phase

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Some interesting instructions

• Saturation
• Bit-counting -- Image coding
• Integer-comparison
• Bit-manipulation
• Seed generation for reciprocal instructions

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Other details

• 64 KB internal program and data
• DMA - peripherals to memory
• Intrinsics in code for better programming
• similar to using ViS in UltraSPARC
• Software pipelining of loops
• PERFORMANCE
• 5-10X
• higher clock -- higher pipeline (2-4X)
• Additional ALUs

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Additional features in C64x

• SIMD support
• Communication-specific instructions
• interleaving, galois field multiply
• Bit count and rotate hardware
• 64 32-bit registers
• Lower resource constraints
• No more NOPs needed ever no boundaries

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C64x DSP Core
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Today

• Background
• Advanced DSP architectures -- TI C6x 15
• Viterbi algorithm basics 10
• Viterbi on TI DSPs 10
• A programmable processor specifically designed
  for Viterbi 15

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Viterbi Decoding
k
n gt k
n
k
Decoder
Encoder
Rate k/n 1/2 Convolutional Encoder
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Error Protection

• States 2(FFs) 2(Constraint Length - 1)
• Cannot go from any state to any state

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Trellis for decoding
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Trellis for an input sequence
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Error detection

• Branch metric Distance between received
  symbol pair and possible symbol pairs
• Path metric Accumulated error metric

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Error-correction
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Stages in Viterbi Decoding

• Calculate Branch metrics for all states every
  stage
• Update Path metrics for all states every stage
• At the end, Traceback the trellis to get the
  decoded bits

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Computations

• Branch metrics
• Hamming distance (XOR) and Count 1s
• Euclidean distance squared distance
• Path metrics
• Add Branch metrics to existing path metrics
• Compare for minimum and Select minimum
• Survivor Traceback
• Linked list /Pointer chasing
• Memory Intensive / Sequential Operations

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Today

• Background
• Advanced DSP architectures -- TI C6x 15
• Viterbi algorithm basics 10
• Viterbi on TI DSPs 10
• A programmable processor specifically designed
  for Viterbi 15

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Viterbi support in different processors

• C54x
• Special hardware accelerator
• ACS unit with 2 ACC and split ALU
• Viterbi butterfly (2 ACS) in 4 cycles
• C62x
• nothing special
• C6416
• Viterbi coprocessor
• K 5-9,Rate 1/2,1/3,1/4

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Viterbi Coprocessor in C6416
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Viterbi Coprocessor in C6416

• SM, SD and HD memory not accessible to DSP

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Today

• Background
• Advanced DSP architectures -- TI C6x 15
• Viterbi algorithm basics 10
• Viterbi on TI DSPs 10
• A programmable processor specifically designed
  for Viterbi 15

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Need for VSP architecture

• Large amount of memory access
• Traceback decoding
• Not efficient on a GPP
• Program instructions in a GPP is of a higher
  order than complexity of the algorithm

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VSP architecture
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Branch Metric Calculation
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Path Metric Calculation
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Traceback Unit
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Traceback with survivor updates
Start Filling the Trellis
5Constraint Length
Start Traceback
Update Survivor Path for most recent symbol
Symbol Decoded
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Survivor Path Updates
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Circular updates
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Software Programming

• Small but specialized instruction set
• LOAD, ACS
• Shorter execution time
• All 3 subprocessors programmed independently
• 10 ns, (100 MHz) in 1990 to get 1.5 Mbps

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Conclusions

• Viterbi algorithm important for implementation in
  a programmable communication receiver
• Approaches have been as co-processor support to
  DSPs or specialized processors.
• We are yet to design programmable processors that
  meet real-time requirements for 100 Mbps
  applications.