ACS Unit of Viterbi Decoder

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ACS Unit of Viterbi Decoder

• Audy ,Garrick Ng, Ichang Wu, Wen-Jiun
  Yong
• Advisor Dave Parent
• Spring 2005

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Agenda

• Abstract
• Introduction
• Project Details
• Results
• Cost Analysis
• Conclusions

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Abstract

• 8-bit ACS unit of Viterbi Decoder
• Clock speed 90 MHz
• Average Power mW
• Average Power Density W/cm2
• Area mm x mm

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Introduction

• commonly used in decoding convolutional codes in
  baseband detection for wireless communication and
  detection of recorded data in magnetic disk
  drives.
• Consist of 3 sections
• BM (branch metric Unit)
• ACS (add-compare-select Unit)
• Survival Path Unit
• ACS unit consumes most power and area, also
  determine the speed of VB

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Project Details

• 8-bit inputs ACS operates at 11ns (90MHz).
• The project was divided into 8 bits CLA adders, 8
  bits subtractor, 21 multiplexer and a register.
  
• Output of the ACS specifics the minimum metric
  path of the two inputs ( A B)

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Architecture of ACS Unit
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Longest Path Calculations
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Schematic
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Layout
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Verification
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Simulations
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Cost Analysis

• Estimated time spent on each phase of the
  project
• Architecture of the design (3 weeks)
• verifying logic (1 week)
• verifying timing (1 week)
• layout (3 weeks)
• post extracted timing (1 weeks)

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Lessons Learned

• Use Cell based design
• Great for debugging passing LVS
• Save time in for multiple bits
• Define a manageable scope of project
• To meet project dateline

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Summary

• We designed an 8-bit ACS unit that operated at
  90 MHz and uses mW of Power and occupied an area
  of mm x mm that can be used in Viterbi decoder
• Future designs can definitely minimize area and
  power.

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Acknowledgements
Do not read this slide, just show it.

• Thanks to our family for putting up with us.
• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Synopsys for Software donation
• Thanks to Professors Parents for his time
  guidance