Viterbi Decoder: Presentation

1
Viterbi Decoder Presentation 3
Overall Project Objective Design of a high speed
Viterbi Decoder
Stage 3 2 Feb. 2004 Size Estimates/ Floorplan

• Omar Ahmad
• Prateek Goenka
• Saim Qidwai
• Lingyan Sun

M1

• Design Manager Yaping Zhan

2
Status

• Design Proposal (finalized)
• Architecture Proposal (done)
• Behavioral -gt Structural Verilog (done)
• Floor-planning and size estimates (done)
• To be done
• Schematics of Design (20 done)
• Component Layout
• Chip Layout
• Spice Simulation of Entire Chip

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Design Decisions Metal Directionality
M1
Metal usage Vdd! M1, M2 Gnd! M1, M2 Internal
Routing M1, M2 Clock M3, M4 Reset M3,
M4 Global Routing M3, M4
M2
M4
M3
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Design Decisions Adders
Ripple-carry
Carry look-ahead
Vs.

• 5 gates/bit
• 34 transistors/bit
• For 8 bits 40 gates
• Easy to implement

• Slightly faster
• Harder logic
• Too big 35 gates/4 bits
• 14,000 transistors
• for all adders in design

Decision? Ripple-carry chosen used Mirror
Adders 28 transistors/bit
18-525, Integrated Circuits Design Project
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Design Decisions Simpler Multiplier
Chosen
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Design Decisions Trace back unit
Place each flip-flop mux pair like this?
Chosen
Or like this?
Too long
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Design Decisions Dealing with Clock skew
Possible ideas

• Tapering
• Buffering
• H-Tree Clock

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Floor Plan Top Level Sizing
650
BCU Unit
40
650
ACS Unit
70
250
170
ML Search
TB Unit
70
140
All units in microns
18-525, Integrated Circuits Design Project
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Floor Plan Top Level Routing
650
clk
BCU Unit
ACS Unit
rst
Buffering/Routing
350
ML Search
TB Unit
All units in microns
18-525, Integrated Circuits Design Project
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Floor Plan Branch Calculation Unit
650
Flip Flops
Flip Flops
..
40
All units in microns
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Floor Plan Add Compare Select Unit
650
Flip Flop
Flip Flop
.
Adder
Adder
.
Subtractor
Subtractor
70
Mux
Mux
.
Flip Flop
Flip Flop
.
All units in microns
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Floor Plan ML Search
8 Bit Subtractor
8 Bit Subtractor
8 Bit Subtractor
8 Bit Subtractor
8 Bit Mux Flop
8 Bit Mux Flop
8 Bit Mux Flop
8 Bit Mux Flop
8 Bit Subtractor
3 Bit Mux Flop
3 Bit Mux Flop
3 Bit Mux Flop
3 Bit Mux Flop
8 Bit Subtractor
8 Bit Mux Flop
8 Bit Mux Flop
3 Bit Mux Flop
3 Bit Mux Flop
8 Bit Subtractor
3 Bit Mux Flop
140
250
All units in microns
18-525, Integrated Circuits Design Project
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Floor Plan Trace Back Unit
Dff
Dff
Dff
Dff

Mux
Mux
Mux
Mux
70
.

Dff
Dff
Dff
Dff
170
All units in microns
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New Transistor Counts
Branch Calculation Unit D-Flip Flops 4
x 17 x 12 8 x 16 x 12
2,352 Adders 4 x 16 x 28
1,792 8 bit
Multipliers 16 x 150
2,400 Total

6,544
Add Compare Select Unit D-Flip Flops 8
x 24 x 12 1 x 8 x 12 2,400
21 Multiplexers 8 x 8 x 14
896 Adders
8 x 16 x 28
3,584 Subtracters 8 x 8 x
29
1,856 Total
8,736
Grand Total 22,402!
Maximum Likelihood Search Unit D-Flip Flops
8 x 6 x 12 3 x 7 x 12
828 21 Multiplexers 8 x 6 x 14 3 x 7
x 14 966 Comparators
8 x 7 x 32
1,792 Adders 4 x 1 x 28
112 Total

3,698
Trace Back Unit D-Flip Flops 8 x 17 x
12 1,632
21 Multiplexers 8 x 16 x 14
1,792 Total

3,424
Key No. of bits x No. of elements x No. of
transistors/bit
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Transistor CountsPrevious Vs. Revised
Previous
Revised
Adders 21 Multiplexers Multipliers Registers
Total
9,136 3,654 2,400 7,212 22,402
5,900 1,056 3,840 2,400 14,196
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Structural Verilog
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Structural Verilog Simulation
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Questions?
18-525, Integrated Circuits Design Project