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Presentation 1: Noise canceling in 1-D data

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Part of a research done in CMU ... This design uses adaptive weighted-frequency ... due to 'physiological hand tremor, jerk, low-frequency wander and also ... – PowerPoint PPT presentation

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Title: Presentation 1: Noise canceling in 1-D data


1
Presentation 1 Noise canceling in 1-D data
  • Seri Rahayu Abd Rauf
  • Fatima Boujarwah
  • Juan Chen
  • Liyana Mohd Sharipp
  • Arti Thumar

M2
2
Overview
  • Part of a research done in CMU
  • Micron Intelligent Microsurgical Instruments
    project led by Prof Pradeep Khosla
  • This design uses adaptive weighted-frequency
    algorithm for noise canceling purposes.

3
Project Background Noise Canceling Chip
  • An essential block in a research project done
    here at CMU Micron Intelligent Microsurgical
    Instrument
  • Main objective of the research
  • To provide a technique to compensate the amount
    of errors due to physiological hand tremor,
    jerk, low-frequency wander and also pathological
    movement disorder.
  • To enhance the accuracy of human-machine
    interfaces.
  • To improve the living of patients with movement
    disorders.
  • To increase performance in microsurgery
    applications.
  • Source http//www-2.cs.cmu.edu/camr/research.ht
    ml

m2
4
Applications
Microsurgery Instrument
Rehabilitation
m2
Image sources http//irb.cs.tu-berlin.de/zuse/hi
story/ibm158c.jpg http//www.richard-wol
f.com/english/e_image/ww_hp4.jpg
5
Applications
Vehicle / Aircraft Maneuvering
Hearing Aid
m2
Image sources http//www.ahaanet.com/hearingaidst
yles.asp http//hometown.aol.com/jaywhle
/extreme/control.gif
6
How does the chip work?
  • It uses adaptive weighted frequency algorithm in
    1-D data.
  • Input Human motion signal with noise
    introduced by pathological and
    physiological tremor.
  • Output Noise suppressed signal for
    higher precision.

m2
7
Block Diagram
Source Modeling and Canceling Tremor in
Human-Machine Interfaces
8
Result
Source Modeling and Canceling Tremor in
Human-Machine Interfaces
9
Transistor Estimate
Part Transistors
8-bit Adders 12x8x24 2304
8-bit Multipliers 10x1200 12000
ROM 800
Registers 10x8x14 1160
Misc 3000
Total 19210
10
Status
  • Design Proposal v
  • Architecture (in progress)
  • To be done
  • Floor Plan
  • Gate Level Design
  • Component Layout
  • Chip Layout
  • Spice Simulation of Entire Chip

11
Problems ?
  • Several inputs are too small for bit shifting
  • (10-7)
  • Value of M could be made greater for higher
    precision (More complex)
  • Transistor count seems too simplereally, it is
    NOT

12
Goal
  • Higher throughput

13
Alternatives
  • Serpent encryption
  • Branch predictor

14
Summary
  • Why do we choose this?

15
Questions?
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