Noise Canceling in 1D Data: Presentation

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Feb 14th, 2005 Gate Level Design
Noise Canceling in 1-D Data Presentation 4
Seri Rahayu Abd Rauf Fatima Boujarwah Juan
Chen Liyana Mohd Sharipp Arti Thumar
M2
Project Manager Bobby Colyer
Overall Project Objective Implementing Noise
Cancellation Algorithm in Hardware
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Status

• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan
• Structural Verilog (Done)
• Revised Floorplan (Done)
• To be done
• Schematics (85)
• Layout (5)
• Spice simulation

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Previous Block Diagram
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Final Block Diagram
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Structural Verilog Output
Behavioral Verilog Output
Structural Verilog Output
Similar Output Values. Differences due to 16-bit
Floating Point Units
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Result Comparison
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New Transistor Count
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Area Estimates
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Revised Floorplan
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Mux 16-bit 21 Layout
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Schematics
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ROM
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Alignment Shifter
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Leading Zero Counter
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Rounding Unit
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Normalizing Unit
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Wallace Tree Multiplier
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Input of ROM Table Testbench
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Test Results for Sine
Time 40ns Input 2.52 (21st value) SinOutput
00110001 0.5823
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Test Results for Cosine
Time 40ns Input 010100 (21st value)
CosOutput 10110101 -0.8130
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Critical Path Estimation

• Cycle 2 will be longer than Cycle 1 because it
  uses 3 FPM 2 FPA while Cycle 1 uses 2 FPM 3
  FPA

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Last weeks challenges

• Finalizing out designs for the floating point
  adders and multipliers
• Wallace tree multiplier vs Array multiplier
• Choose Wallace implementation because it saves
  10 of power
• Leading zero counter for normalizing block
• Found a smaller implementation of the normalizing
  block

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This weeks challenges

• Completing and Testing Top level Schematic
• Creating Layouts for Floating Point Multipliers
  and Adders with different shapes
• Clock Skew and other Timing issues
• Transistor count ?.. again..

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Questions?