Noise Canceling in 1D Data: Presentation

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Feb 23rd, 2005 Functional Layout/Floorplan
Noise Canceling in 1-D Data Presentation 6
Seri Rahayu Abd Rauf Fatima Boujarwah Juan
Chen Liyana Mohd Sharipp Arti Thumar
M2
Project Manager Bobby Colyer
Overall Project Objective Implementing Noise
Cancellation Algorithm in Hardware
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Status

• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
• - Schematics (Done)
• To be done
• Layout (28)
• Spice simulation

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Design Decisions

• Compared the performance of the mirror adder with
  the our Mux-Adder
• Area vs Speed
• Discovered that they have the same size, so stick
  to the original one
• 2. Decided to implement Booth Recoding for the
  Wallace tree multiplier
• Need more testing

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Last Monday
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Today
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Functional Block Layout
ROM Table
Output to converter
Input from counter
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Tentative Layout for Fixed Point Multiplier (aka
the Wallace)
Right Tree
Left Tree
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Pseudo-Layout for the fpAdder
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Improved Half Adder
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Improved Full Adder
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Alternative Mirror Adder
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Completed 16 bit 2-1 Mux
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Challenges

• Booth
• Revision to Floorplan due to optimized layout of
  the functional blocks

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Questions?