Nessun titolo diapositiva

1
Rout di un CMOS
Con Vcc 4.5 V I0 4.0 mA
Typ 0.15 V 25 oC Max Full range 0.33 V -
40?85 oC
VOL
Eq.(2.62)
2
Con Vcc 4.5 V I0 - 4.0 mA
Typ 4.32 V 25 oC Min Full range 3.84 V -
40?85 oC
VOH
Eq.(2.63)
3
CMOS Fan Out
Ii molto piccola
F. O. non limitato
Velocità di commutazione ad alta f influenzata
dalle Ci
tri limite
WORST CASE 60MW
Eq.(2.64)
4
Eq.(2.65)
Vo, Vi e Ci possono assumere valori diversi a
seconda del worst case che si deve considerare
(T,Vcc, ecc.). Con n CMOS
Eq.(2.66)
5
Eq.(2.67)
Eq.(2.68)
con
Eq.(2.59)
6
Con VIH 3.15 V e VOH 4.4 V
nMAX 505
Ogni HCMOS aggiunge un ritardo di
che corrisponde a
Eq.(2.70)
7
Famiglie HCMOS (74HC)
D1,Q1 e Q2 sono per le scariche statiche e per il
clamp. C1 e C2 sono le capacità parassite di GATE.
C1 C2TYP 5 pF
8
Interfaccia TTL
VOHCMOS compatibili con VITTL
VOH 4.45 V VIH 2 V VOL 0.1 V
VIL 0.8 V
D1 2.45 V
9
(No Transcript)
10
Interfaccia CMOS TTL
CMOS HCMOS, ACL TTL LS,AS/F/ALS
Senza carico
CMOS
Eq.(3.1)
TTL
Eq.(3.2)
Col carico può solo peggiorare
11
HC TTL
I livelli di tensione compatibili, ma le correnti
in gioco sono diverse
Limiti sul Fan-Out
FAN OUT 2
12
TTL HC
VOL compatibile con VIH
ma
VOH 2.4 ? 2.7 V e VIH 3.5 V (a Vcc 5V)
Eq.(3.3)
1 non garantito
(in realtà sono i worst case)
13
TTL HCMOS
14
Eq.(3.4)
con
Vccmin 4.75 V, VOLMTTL 0.4 V IOLTTL 16
mA, IILHC -1 mA
Rpmin fornisce una IOL supplementare a Q3
Non deve alzare VCE oltre VOL
15
Eq.(3.5)
con
VccM 5.25 V, VIHminHC 0.4 V IIH HC 1 mA,
IOH TTL -400 mA
16
Quando Vo sale Q2 OFF
V deve caricare la capacità parassita (10 pF)
tramite RP
t RPCi entro trMAX
17
LSTTL HCMOS
Rpullup
18
CMOS ALSTTL
Livelli compatibili
Quando A è a 0 cè una IIH 0.1 mA che esce
dalla base della ALSTTL.
Ma IOH(CMOS) 4 mA
FAN OUT 40
19
ALSTTL CMOS
Rpullup
Livelli H incompatibili
CMOS ASTTL
Livelli compatibili
IIL(ASTTL) 2 mA IOL(HC) 4 mA
FAN OUT 2
ASTTL CMOS
Rpullup
Livelli H incompatibili
20
Advanced CMOS LOGIC (ACL)
tpd 5 ns ( 8 ns per HC)
Io 24 (mA) ( 4 mA per HC)
21
(No Transcript)
22
(No Transcript)
23
Benefits of Bipolar CMOS BiCMOS
BICMOS

Low power consumption Ideal technology for VLSI
circuits
CMOS


High circuit speed High drive capability (bus
interfaces !) High-performance analog
circuits Improved ESD protection
Bipolar



24
BICMOS Inner Circuitry
CMOS input
Bipolar output
5 V - TTL Input/Output Signals
no 3-state or protection circuitry shown
25
Simultaneous Switching with Bipolar and BiCMOS
Logic
SN74F245
SN74ABT245
Critical with F/AS in poor designs
Not critical with BCT/ABT/LVT
26
Output Edge Control Circuitry (OEC)

• Gradual turn-on of output transistors by
  splitting the output in multiple stages
• Dynamic smoothing circuit by softening the
  turn-on to obtain gradual takeover of current
  (di/dt control)

Vcontrol
VCC
VO
The result is that ground bounce is almost
independent of the load!
T1
T2
T3
GND
OEC is a trademark of Texas Instruments
Incorporated
27
Advanced 5 V LogicOutput Characteristics (Drive
capability)
28
Static Power Consumption Application Example
29
Logic FamiliesPower vs Frequency Comparison
245/16245 TYPE SINGLE OUTPUT SWITCHING CLoad
50 pF
'AC11245
70.0 mW
60.0 mW
'F245
50.0 mW
40.0 mW
'ABT245
'LV244
30.0 mW
'LVT245
20.0 mW
'LVC245
AHC244
Vcc5V
10.0 mW
ALVC16244
AHC244
Vcc3.3V
0.0 mW
0 MHz
10 MHz
20 MHz
30 MHz
40 MHz
50 MHz
Frequency (MHz)
30
Why 3.3 V ?
Vcc Icc
(
)
(
)
PTOT Vccx Icc x - CL x
NSW x fO x fI x NSW ? (CLn fOn)
fI VCC
where
Theroretically 5V
3.3 V PTOT
- 34 1)
Practically 5V
3.3 V
PTOT - 50-70 2)
1) assume that Output-Levels VOL and VOH are
maintained
2) assume that Output-Level VOH is changing to
3.3 V
31
2 Factors driving Lower Voltage
1. Power Dissipation 2. Process Geometry
Speed / Power Dissipation vs Vcc
Process Geometry vs VCC
Relative Power ()
Relative Speed ()
30
120
120
TTL
25
100
100
Speed
Maximum VCC with no Reliability Problem
80
80
15
High VTH
Power
60
60
10
74F
Classic5V VCC
Modern3.3V VCC
40
40
0.8?
5
0.6?
0.5?
20
20
1970
1980
1990
0.35?
3
4
5
2
6
Supply Voltage (V)
32
Logic Families for 5V and 3.3V
high speed, medium drive
medium speed, medium drive
high speed, high drive
low speed, low drive
HC/HCT
F AC/ACT
ABT
FCT-C
5V
5V
5V
5V
3.3V
3.3V
3.3V
3.3V
LV
LVC
LVT
ALVC
33
LVT / LVC / ALVC / LV Comparison
Product Family
SN74LVT
SN74LVC
SN74ALVC
SN74LV
tpd(typ) 2.4ns
tpd(typ) 4.0ns
tpd(typ) 2.1ns
tpd(typ) 8.0ns
Speed 245 type
tpd(max) 4.0ns
tpd(max) 6.5ns
tpd(max) 2.9ns
tpd(max) 14.0ns
IOH -32mA
IOH -24mA
IOH -24mA
IOH -8mA
Drive
IOL 64mA
IOL 24mA
IOL 24mA
IOL 8mA
Current consumption
ICCH/Z 190
?
A
ICCH/Z 10
?
A
ICCH/Z 40
?
A
ICCH/Z 20
?
A
ICCL 5mA
Vcc range
Vcc 2.7
- 3.6 V
Temperature range
-40 ... 85
degrees Celcius
Switching noise
Ground-Bounce less
than 800 mV
Package
SOIC / SSOP / TSSOP
SOIC / SSOP / TSSOP
SSOP /TSSOP
SOIC / SSOP / TSSOP
ABT
AC
FCT
HC
Price Similarity
?
?
?
Special user benefit
Bus hold cells
Very low noise
Bus hold cells
Very low noise
??
??
??
??
High impedance
5V tol. I/O
Very low noise
??
??
??
??
Specification at Vcc5V available
at power down
?
??
??
pure 3.3 V
Broad product spectrum incl. Gates/FF/MSI...
Very low noise
??
??
5V tol. I/O
34
3V and 5V TTL and CMOS Specifications
VCC 4.5 - 5.5V
VCC 5 V
TTL levels
Low Voltage levels
CMOS levels
VCC 2.7 - 3.6V
V
VTH 2.5V
VOH 2.4V
VOH 2.4V
VIH 2.0V
VIH 2.0V
VTH 1.5V
VTH 1.5V
VIL 1.35V
VIL 0.8V
VIL 0.8V
VOL 0.5V
VOL 0.4V
VOL 0.1V
35
5 Volt 3.3 Volt Interfacing LV and ALVC
5V
5V
3.3V
Any TTL or CMOS Family
Bipolar TTL orHCT/ACT
LV/ALVC
LV/ALVC
5V CMOS
HC
TTL
VCC 0.5 max
Bipolar TTL
3.3V CMOS
2V
2V
0.8V
0.8V
not possible
not advised
36
5 Volt 3.3 Volt Interfacing LVT and LVC
5V
5V
3.3V
Any TTL or CMOS Family
Bipolar TTL orHCT/ACT
LVC/LVT
LVC/LVT
TTL
HC
5V CMOS
5.5V
3.3V CMOS
Bipolar TTL
2V
2V
0.8V
0.8V
not advised

• LVCxxxA and LVT devices allow direct interface
  from 5V TTL- and 5V CMOS - devices
• The direct interfacing to 5 V CMOS is not
  adviced

37
Special Level Shifters LVC4245 and ALVC164245
4245 pinning
245pinning
The dual VCC level shifters ALVC164245 and
LVC4245 have 3.3V and 5V VCC pins (dual VCC) In
this way, a full mixed mode system can be
designed.
VCCA
VCCB
DIR
A0 . . . B7
B0 . . . B7
4245
164245
GND
GND
GND
This solution is compatible with a 3.3V-only
system Both can be replaced later with 3.3V
parts without PCB redesign
38
Bidirectional Interface
Vcc 5 V
3 V System
5 V CMOS System
CBTD
1N4148
CBT
In/Out
5 V CMOS System
LV LVC LVT ALVC

• ?P
• ?C
• DSP

• RAM
• ASICS

• Crossbar Switches (CBT) are high-speed bus
  connect devices with rdson 5???
• Each switch consists of a N - channel MOS
  transistor.
• The diode drop of 0.7V and the gate to source
  drop of 1V brings the input voltage of the 3 V
  logicto a 3.3 V Level .
• Crossbar Switches with integrated diode (CBTD)
  are available from Texas Instruments