ECE 426 VLSI System Design

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ECE 426 - VLSI System Design

• Lecture 12 - Timing, Project Overview

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Exam 1 - Take-Home
• Out March 24
• Due March 31
• Timing References
• Synopys Online Documentation (SOLD) Manuals
  -access using the "sold" command
• Design Compiler User Guide
• Design Compiler Tutorial
• Design Compiler Reference Manual
• Pran Kurup and Taher Abbasi, Logic Synthesis
  using Sysnopsys, 2nd ed., Kluwer Academic
  Publishers, 1997.

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Where we are...

• Last Time
• State Coding Assignment
• Timing
• Today
• Timing in Synopsys Tools
• Project Overview

4
Timing in the Design Compiler

• DC assumes a synchronous, clock-based system
• Derives setup, hold constraints between registers
• User-specified timing constraints on inputs,
  outputs

Comb. Logic (Internal)
Comb. Logic (Output)
Comb. Logic (Input)
D
Q
D
Q
D
Q
D
Q
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Specifying Timing in Synopsys DC

• Clock specification (See last lecture slide
  37-38)
• Period
• Skew (and uncertainty)
• Input constraints
• Output constraints
• Combinational delay constraints
• Special cases
• false paths
• multicycle paths

6
Input Constraints A Closer Look

• Rationale
• assume input is tied to some "other" module
• input delay output delay of other module
• Example
• set_input_delay 17 -clock clk d1

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Input Constraints A Closer Look

• Impacts delay of input logic (of current design)
• Creates maximum timing constraint for setup time
• Creates minimum timing constraint for hold time

clk
d1
17 ns
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Output Constraints A Closer Look

• Rationale
• assume output is tied to some "other" module
• output delay input delay of other module
  setup time
• Example
• set_output_delay 5 -clock clk d1

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Output Constraints A Closer Look

• Impacts delay of output logic (of current design)
• Creates maximum timing constraint for setup time
• Creates minimum timing constraint for hold time

tco
tpff
15 ns
comb. logic
clk
comb. logic
D
Q
output logic
d2
D
Q
d2
clk
5 ns
"other" module
"current design" module
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Timing Constraints Example

• VHDL Code
• library ieee
• use ieee.std_logic_1164.all
• entity timing_ex is
• port( a, b, clk, reset in std_logic
• d out std_logic )
• end
• architecture behavior of timing_ex is
• signal f std_logic
• begin
• process (clk, reset)
• begin
• if (reset '0') then f lt '0'
• elsif (rising_edge(clk)) then f lt a
• end if
• end process

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Timing Constraints Example

• Timing Constraints
• create_clock clk -period 10.0
• set_fix_hold clk / check hold time /
• set_input_delay 0.5 -clock clk a,b
• set_output_delay 1.0 -clock clk d
• Synthesized Design

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Getting Timing Reports

• Seeing timing results report_timing
  command report_timing -max_paths 5
• Result
• Report timing
• -path full
• -delay max
• -max_paths 5
• Design timing_ex
• Version 2000.05-1
• Date Thu Apr 5 152605 2001
• Operating Conditions
• Wire Load Model Mode top
• (continued)

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Timing Report - Register to Register

• Startpoint f_reg (falling edge-triggered
  flip-flop clocked by clk')
• Endpoint d_reg (falling edge-triggered
  flip-flop clocked by clk')
• Path Group clk
• Path Type max
• Point Incr
  Path
• ------------------------------------------------
  -----------
• clock clk' (fall edge) 0.00
  0.00
• clock network delay (ideal) 0.00
  0.00
• f_reg/CLK2 (dfrf301) 0.00
  0.00 f
• f_reg/Q (dfrf301) 1.04
  1.04 f
• U32/O2 (nanf211) 0.30
  1.33 f
• d_reg/DATA1 (dfrf301) 0.00
  1.33 f
• data arrival time
  1.33
• clock clk' (fall edge) 10.00
  10.00
• clock network delay (ideal) 0.00
  10.00
• d_reg/CLK2 (dfrf301) 0.00
  10.00 f
• library setup time -0.26
  9.74

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Timing Report - Output Logic

• Startpoint d_reg (falling edge-triggered
  flip-flop clocked by clk')
• Endpoint d (output port clocked by clk)
• Path Group clk
• Path Type max
• Point Incr
  Path
• ------------------------------------------------
  -----------
• clock clk' (fall edge) 0.00
  0.00
• clock network delay (ideal) 0.00
  0.00
• d_reg/CLK2 (dfrf301) 0.00
  0.00 f
• d_reg/Q (dfrf301) 0.97
  0.97 f
• d (out) 0.00
  0.97 f
• data arrival time
  0.97
• clock clk (rise edge) 10.00
  10.00
• clock network delay (ideal) 0.00
  10.00
• output external delay -1.00
  9.00
• data required time
  9.00
• ------------------------------------------------
  -----------

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Timing Report - Input Logic

• Startpoint a (input port clocked by clk)
• Endpoint f_reg (falling edge-triggered
  flip-flop clocked by clk')
• Path Group clk
• Path Type max
• Point Incr
  Path
• ------------------------------------------------
  -----------
• clock clk (rise edge) 0.00
  0.00
• clock network delay (ideal) 0.00
  0.00
• input external delay 0.50
  0.50 f
• a (in) 0.00
  0.50 f
• f_reg/DATA1 (dfrf301) 0.00
  0.50 f
• data arrival time
  0.50
• clock clk' (fall edge) 10.00
  10.00
• clock network delay (ideal) 0.00
  10.00
• f_reg/CLK2 (dfrf301) 0.00
  10.00 f
• library setup time -0.23
  9.77
• data required time
  9.77

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Other Timing Constraint Functions

• Tell timing analyzer to ignore a false
  path set_false_path -from source -to dest
• Specify combinational delays set_min_delay amt
  -from source -to dest set_max_delay amt -from
  source -to dest
• Specify multicycle path of N cycles set_multicylc
  e_path N -from source -to dest

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How DC Works With Constraints

• Compile (Optimization) Steps
• Initial mapping to gates in library
• Delay optimization attempt to fix constraint
  violations
• Design rule fixing attempt to fix design rule
  violations
• Area optimization attempt to meet area
  constraints without creating timing violations
• What happens when DC can't meet constraints
• Apply flattening (if you can afford to)
• Re-work constraints

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Using DC With Large Designs

• DC can't optimize large designs as one unit
• Typical approach use hierarchy to control
• Control runtime
• Control optimization strategy

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Using DC With Large Designs (cont'd)

• Compilation strategies
• Top-down - compile all submodules together
• Bottom-up - compile leaf modules first, then move
  up(use "characterize" commands to get input,
  output delays)
• Mixed - use different approaches as appropriate
  in different levels of hierarchy

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Timing in Design Flow - ASIC Design
START
Design Compiler
Synthesize Blocks / Timing Analysis
Timing OK?
N
Y
Place Route / Timing Analysis
Timing OK?
N
Y
DONE
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Project Overview - WimpNet03

• Key idea computers communicate on shared wires
  (ether)
• Each computer has 8-bit address
• Information passed as packets

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Packet Format

• Header
• destination address (8 bits)
• source address (8 bits)
• length (8 bits)
• Data - up to 255 bytes
• CRC Byte - Error Code

All bytes transmitted with LSB first
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Control Procedure - CSMA/CD

• CSMA/CD
• Carrier Sense Multiple Access with Collision
  Detection
• Procedure
• Defer - dont transmit when carrier sense
• Transmit - transmit while monitoring data
• Collision - error in transmission when two
  stations transmit at same time
• Abort - terminate transmission and jam 4-6 bytes
• Backoff - wait for a random retransmission delay
• Retransmit - try again after backoff

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Project Goals

• Build a complete WimpNet03 Interface Chip
• Receiver with buffer RAM
• Transmitter with buffer RAM
• Area budget 4 MOSIS Tiny Chips (4400l X 4400l)

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Transmitter Details
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Receiver Details
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RAM Subsystem Details

• Two-port organization
• Write port - writes on falling edge of clk when
  w_en_lL
• Read port
• Size 256 Bytes

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Design Groups

• Receiver Design
• Transmitter Design
• RAM Subsystem Design
• Chip assembly

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Coming Up

• More about the Project
• Subsystem Design RAM