VLSI Design and Test Automation Research

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VLSI Design and Test Automation Research

• F. Beyette, H. Carter, W. B. Jone,
• C. Purdy, K. Tomko, R. Vemuri, P. Welsey

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Focus

• Design, analysis, and test of integrated circuits
  and systems.
• Digital, analog, mixed signal and mixed
  technology microchips and systems.
• Applications to computing, communication, and
  embedded processing.
• VLSI systems education.

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Existing Research Strengths

• Design
• Digital and analog microchip design
• FPGA-based reconfigurable systems
• Mixed signal, mixed technology systems
• (opto-electro-mechanical microsystems)
• Test architectures, design-for-testability
• Low power design
• Design Automation and CAD
• Automated design synthesis
• Discrete and continuous simulation
• Test pattern generation
• Analysis, benchmarking, experiment design
• Hardware description languages, VHDL
• Distributed/parallel computing and CAD methods

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Visibility and Impact

• 150 journal, 410 conference papers since 90
• 3 books and 30 book chapters
• 7 Best Paper awards
• Editorships
• IEEE Transactions on VLSI
• IEEE Potentials
• Transactions on Modeling and Simulation
• Journal of VLSI Design
• IEEE Computer (guest)
• General/program/panel chairs of numerous
  conferences (30 since 95)

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Industry Employers of Our Graduates

• Intel
• Xilinx
• Motorola
• Hewlett-Packard
• Honeywell
• Sun Microsystems
• LSI Logic
• Digital-Compaq-Intel
• Lucent
• AT T
• Qualcom

• Cadence
• Synopsys
• Mentor Graphics
• NeoLinear
• FTL Systems
• Simplex
• Matrix
• Symbios
• Fore Systems
• Oracle
• Microsoft
• EDAptive

• 45 PhDs and 120 Masters graduated since 1990.
• 30 PhDs and 45 Masters in progress.

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Past Sponsors of Our Research

• DARPA (MTO, ITO, DSO)
• AFRL (SN, IF, and Mantech at WPAFB and GAFB)
• Semiconductor Research Corporation
• National Science Foundation
• National Security Agency
• DAGSI
• NASA
• Industries (GE, TI, Xilinx, TRW, Raytheon, Sun,
  MTL, FTL, EDAptive.)
• Several SBIRs (8 Phase II and many more Phase I)

Total 15M since 1990.
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Government Lab Collaborators

• Sandia National Lab
• NASA Langley
• NASA Lewis
• AFRL, Sensors Directorate
• AFRL, Information Directorate
• Rome Research Institute, GAFB
• JPL

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Educational Grants/Contracts

• NSF (VLSI minor program and VLSI Design and Test
  Lab)
• NSF (combined research and education)
• DARPA (RASSP educator and facilitator contract)
• DARPA (ADA education)
• Several graduate fellowships (SRC, OBR etc.)
• MOSIS (About 10K/year since 1991 for microchip
  fabrication. About 250 microchips, each with
  15,000-20,000 transistors, were fabricated and
  tested.)
• Xilinx (hardware donations, over 300K)
• Altera (hardware and software donations)
• Cadence, Synopsys, Xilinx etc. (CAD software
  donations worth several M)

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Multichip Synthesis

• How to partition a large
• specification and synthesize
• a multichip design using the
• available package options?

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Multichip Synthesis System, MSS

• Viper multichip module design was
• automatically synthesized using
• the MSS CAD system.
• Viper is a RISC microprocessor.
• To accomplish this, the MSS system
• was successfully integrated with
• many commercial CAD systems.

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VASE Mixed Signal Synthesis System
Functional Specification in VHDL-AMS
Performance Goals
Analog/Digital Partitioning
Analog Component Library
Digital Component Library
Layout Integration
Digital Layout
Analog Layout

• VASE research
• nominated for Best Paper
• Award at DATE99

Mixed Analog-Digital Layout
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Multi-Channel Voice Transmitter-ReceiverSynthesiz
ed Using VASE
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A Plugin Architecture for Linking CAD Tool
Backends to a VHDL Frontend

• Philip A. Wilsey
• Experimental Computing Lab

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SAVANT
VHDL '93 VHDL-AMS VHDL-2001
SAVANT VHDL analyzer/code generator TyVIS C
Code Generator VHDL simulation kernel WARPED
Discrete-event simulation kernel
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Extension by Inheritance
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Extensibility through Cloning
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The Clone Step
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Prof. C. Purdy-- Digital Design Research

• 1. Sensor data processing and systems-on-a-chip
• 2. Evaluation of CAD algorithms

--Improved accuracy and speed --Smaller circuits

• Circuits Systems Design Laboratory

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Network on Chip (NoC)

• On chip communication with a network is very
  simple and reliable
• Routers are used to direct
• the flow of communication
• Predictable electrical
• parameters enable
• high performance circuits
• Enables the use of fault tolerant wiring and
  protocols
• Facilitating reuse with a universal interface and
  also extending the reuse to network

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MEMS BIST and BISR
Capacitance partition of dual-mode BIST solution
Mites crawl on MEMS gears
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Importance of Embedded Memory Testing / Diagnosis
/ Repair

• Source ITRS 2001 Percentage of Logic Forecast
  in SoC Design

Year Node (nm) Area New Logic Area Reused Logic Area Memory
1999 180 64 16 20
2002 130 32 16 52
2005 100 16 13 71
2008 70 8 9 90
2014 35 2 4 94
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Interconnect Noise Testing for High-Speed Deep
sub-Micron VLSI circuits

• Deal with signal integrity problem due to
  cross-coupling capacitance and inductance in long
  interconnects
• Circuit speed in the level of GHZ
• Hard to accurately model the behavior of coupling
  capacitance and inductance for deep-submicron,
  high-speed (GHZ) circuits
• Try to use pseudo-exhaustive built-in self-test
  to solve the problem