ECE 426 VLSI System Design

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ECE 426 VLSI System Design

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Title: ECE 426 VLSI System Design

1
ECE 426 - VLSI System Design

Lecture 2 - Verilog Review
January 29, 2003

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2
Where we are...

Today
Verilog Review
Verilog, Event-Driven Simulation, and Delays

3
Announcements

Class in AEC 400 until further notice
TA Position Available in ECE 323 Lab- See Dr.
Rich
Reading
Wolf 8.1-8.3
Breaking news
Smaller chip companies combine efforts on new
processes
EE Times 1/13 AMD, IBM to collaborate on 65nm,
45nm
EE Times 1/20 Motorola, Philips
STMicroelectronics collaborating on 90nm 65nm
development
Intel continues to go it alone (EE Times 1/20)

4
Major Topics this Semester

Advanced Verilog
Verilog Review
Event-Driven Simulation
Delays
Coding Styles for Synthesis and Large Designs
Behavioral Modeling
Testbenches and Verification
More about Chip Design
Group Design Project Simplified Ethernet Design
and Verification (WimpNet 03)

5
Review - ASIC Design Flow
6
Verilog Review

Basic Module Syntax
Combinational Logic
Parameters
Module Instantiation
Sequential Logic
Finite State Machines

7
Verilog Background

Designed as a language for event-driven
simulation
Synthesis added as an afterthought
Only a subset can be synthesized
Synthesis tools try to match simulation behavior
So far, weve focused on the synthesis subset
Structural Descriptions - module instantiations
Behavioral Descriptions
assign - continuous assignments
always blocks

8
Verilog module construct

Key building block of language
declaration - specifies a module interface
Input output ports connections to outside world
black box model - no details about internals
body - specifies contents of "black box"
behavior - what it does
structure - how it's built from other "black
boxes"

9
Verilog Module Declaration

Describes the external interface of a single
module
Name
Ports - inputs and outputs
General Syntax
module modulename ( port1, port2, ... )
port1 direction declaration
port2 direction declaration
reg declarations
wire declarations
module body - parallel statements
endmodule // note no semicolon () here!

10
Verilog Body Declaration - Parallel Statements

Parallel statements describe concurrent behavior
(i.e., statements which execute in parallel)
Types of Parallel Statements
assign - used to specify simple combinational
logic
always - used to specify repeating behavior for
combinational or sequential logic
initial - used to specify startup behavior (not
supported in synthesis - but useful in
simulation!)
module instantiation - used for structure
and other features useful only in simulation

11
Verilog Data Types

nets - describe wire connections
general purpose wire
special purpose supply0, supply1, tri0,
tri1, triand, trior, trireg, wand, wor
registers - variables (assigned values by
procedural statement)
reg - basic binary values
integer - binary word (32 bits - machine
dependent)
real - floating point (not supported by
synthesis)
time - simulation time (not supported in
synthesis)
realtime - simulation time (not supported in
synthesis)

12
Verilog Logic Values

Each wire or register type can take on 4 values
0 - Standard binary FALSE
1 - Standard binary TRUE
X - UNKNOWN
Z - High Impedance
During simulation, all variables originally X
Complication x z sometimes used as wildcards
(e.g. casex, casez)

13
More about Data Types

Vectors - Multiple-Bit Signals (net or register)
wire 310 sum
reg 70 avg
Arrays - used for memories
reg 70 memory 0255
Strings - vector sized to hold ASCII constant
a string

14
Data Types and Module Ports

Input ports must always be a wire (net)
Output ports can be wire or reg

wire
reg
wire
wire
wire
wire
15
Comb. Modeling with assign

Used for simple logic functions
module fulladder(a, b, cin, sum, cout)
input a, b, cin
output sum, cout
assign sum a b cin
assign cout a b a cin b cin
endmodule

16
Combinational Modeling with always

Motivation
assign statements are fine for simple functions
More complex functions require procedural
modeling
Basic syntax
always (sensitivity-list)
statement
or
always (sensitivity-list)
begin
statement-sequence
end

17
Combinational Modeling with always

Example 4-input mux behavioral model
module mux4(d0, d1, d2, d3, s, y)
input d0, d1, d2, d3
input 10 s
output y
reg y
always _at_(d0 or d1 or d2 or d3 or s)
case (s)
2'd0 y d0
2'd1 y d1
2'd2 y d2
2'd3 y d3
default y 1'bx
endcase
Endmodule

18
Review Questions

What are these pitfalls?
Latch Inference
Missing inputs on sensitivity list

19
Modeling with Hierarchy

Create instances of submodules
Example Create a 4-input Mux using mux2 module
Original mux2 module
module mux2(d0, d1, s, y)
input 30 d0, d1
input s
output 30 y
assign y s ? d1 d0
endmodule

20
Modeling with Hierarchy

Create instances of submodules
Example Create a 4-input Mux using mux2 module
module mux4(d0, d1, d2, d3, s, y)
input 30 d0, d1, d2, d3
input 10 s
output 30 y
wire 30 low, high
mux2 lowmux(d0, d1, s0, low)
mux2 highmux(d2, d3, s0, high)
mux2 finalmux(low, high, s1, y)
endmodule

21
Parameterized Modules

Parameters - define values that can change
Declaration
module mod1(in1, in2, out1, out2)
parameter Ndefault-value
input N-1 0 in1, in2
output N-1 0 out1
endmodule
Instantiation
wire 70 w, x, y
wire z
mod1 (8) my_mod1(w,x,y,z)

22
Parameterized Modules Example

N-bit 2-1 multiplexer (parameterized bitwidth)
module mux2( sel, a, b, y )
parameter bitwidth32
input sel
input bitwidth-10 a, b
output bitwidth-10 y
assign y sel ? b a
endmodule
Instantiations
mux2 (16) my16bit_mux(s, a ,b, c)
mux2 (5) my5bit_mux(s, d, e, f)
mux2 (32) my32bit_mux(s, g, h, i)
mux2 myDefault32bit_mux(s, j, k, l)

23
Symbolic Constants with Parameters

Idea use parameter to name special constants
parameter RED_ALERT 2b11
parameter YELLOW_ALERT 2b01
parameter GREEN_ALERT 2b00
Dont change in module instances
Do this to make your code more understandable
For others reading your code
For yourself reading your code after some time
has passed

24
Sequential Design in Verilog - Basic Constructs

Describe edge-triggered behavior using
always block withedge event
always _at_(posedge clock-signal)
always _at_(negedge clock-signal)
Nonblocking assignments (lt)
_at_always(posedge clock-signal)
begin
output1 lt expression1
. . .
output2 lt expression2
. . .
end

25
Combining Sequential and Combinational Outputs

General circuit - both registered and comb.
outputs
Approach multiple always blocks or assign
statements

26
Example Adding carry to 4-bit Counter

module counter(clk, Q, carry)
input clk
output 30 Q
output carry
reg 30 Q // a signal that is assigned a
value
assign carry (Q 4'b1111)
always _at_( posedge clk )
begin
Q lt Q 1
end
endmodule

27
Review Question What Happens Here?

module counter(clk, Q, carry)
input clk
output 30 Q
output carry
reg 30 Q // a signal that is assigned a
value
reg carry
always _at_( posedge clk )
begin
carry lt (Q 4'b1111)
Q lt Q 1
end
endmodule

28
State Machine Design

Traditional Approach
Create State Diagram
Create State Transition Table
Assign State Codes
Write Excitation Equations Minimize
HDL-Based State Machine Design
Create State Diagram (optional)
Write HDL description of state machine
Synthesize

29
Coding FSMs in Verilog - Explicit Style

Clocked always block - state register
Combinational always block -
next state logic
output logic

30
Coding FSMs in Verilog - Code Skeleton

Part 1 - Declarations
module fsm(inputs, outputs)
input . . .
input . . .
reg . . .
parameter NBITS-10
S0 2'b00
S1 2'b01
S2 2b'10
S3 2b'11
reg NBITS-1 0 CURRENT_STATE
reg NBITS-1 0 NEXT_STATE

31
Coding FSMs in Verilog - Code Skeleton

Part 2 - State Register, Logic Specification
always _at_(posedge clk)
begin
CURRENT_STATE lt NEXT_STATE
end
always _at_(CURRENT_STATE or xin)
begin
case (CURRENT_STATE)
S0 . . . determine NEXT_STATE, outputs
S1 . . . determine NEXT_STATE, outputs
end case
end // always
endmodule

32
Verilog and Event-Driven Simulation

Key idea model circuit operation as sequence of
events that take place at specific times
Input events - when input changes
Output events - response to input events (only
generated when output changes)

33
Event-Driven Simulation

Example Modeling and AND Gate
Input events changes on A, B input net
Output events changes on C output net after
delay

A
delay12
A
B
C
B
C
34
Event-Driven Simulation

Output events from AND input events for OR
Simulation time jumps from event to event

A
delay3
B
A
D
delay4
C
B
E
C
D
E
35
Notes about Event-Driven Simulation

Why use event-driven simulation? Because it's
fast
Only model when signals change
Loss of accuracy assumes ideal logical behavior
What are the alternatives?
Circuit simulation (e.g. PSpice)
Numerical model of continuous behavior
More accurate, but slower
Cycle-Level Compiled code simulation
Model behavior in each clock cycle
Faster, but doesnt model dlay

36
Event-Driven Simulation (cont'd)

Processing Events - Data Structures
Event - specifies
time event will occur
net where signal will change
new value of net
Event Queue - data structure that sorts events by
time
front of queue - earliest event
back of queue - latest event
also called a timing wheel

37
Event-Driven Simulation - Algorithm

Processing Events - Simulation Algorithm
initialization set all nets regs to x
while (event queue not empty)
current_event "earliest" event in queue
current_time current_event.time
current_event.net.value current_event.value
for (each module input connected to net)
evaluate(module) if output of module
changes create new event to represent
output change add new event to queue

38
Verilog Simulation Model

assign statement
executes when event changes any input
produces output event when output values changes
always block
executes when event changes variable in
sensitivity list
produces output events when outputs change

39
Coming Up

Delay Modeling in Verilog
Other Verilog Features
tasks functions
system tasks
Verilog coding styles
Behavioral Modeling
Testbenches and Verification

40
Outline - Introduction to Verilog

Goals of HDL-Based Design
Verilog Background
A First Example
Module and Port Declarations
Modeling with Continuous Assignments
Some Language Details
Modeling with Hierarchy
Modeling with always blocks (combinational logic)
Demonstration Using Verilogger
Discuss Project 1
Summary

41
HDL Overview

What is an HDL? A language for
simulation - event driven model of execution
synthesis - generates designs that match
simulated behavior for a subset of the language
Common HDLs
Verilog HDL
VHDL - VHSIC (Very High-Speed IC) HDL
SystemC - C with class libraries to support
System-Level Design and Hardware Design

42
Verilog Simulators

On Windows Machines Synapticad Verilogger
(formerly veriwell)
Available on PCs in DSP Electronics Labs
OR download from class website
OR borrow CD
To run Programs-gtSynapticad/Verilogger Pro
On the Sun Workstation Synopsys vcs / virsim
vcs -RI
On Windows NT Machines Cadence Verilog
Installed, but havent used yet

43
Verilog module construct

Key building block of language
declaration - specifies a module interface
Input output ports connections to outside world
black box model - no details about internals
body - specifies contents of "black box"
behavior - what it does
structure - how it's built from other "black
boxes"

44
A First Example

Full Adder
module fulladder(a, b, cin, sum, cout)
input a, b, cin
output sum, cout
assign sum a b cin
assign cout a b a cin b cin
endmodule

45
Comments about the First Example

Verilog describes a circuit as a set of modules
Each module has input and output ports
Single bit
Multiple bit - array syntax
Each port can take on a digital value (0, 1, X,
Z)during simulation
Three main ways to specify module internals
Continuous assignment statements - assign
Concurrent statements - always
Submodule instantiation (hierarchy)

46
Bitwise Operators

Basic bitwise operators identical to C/C/Java
module inv(a, y)
input 30 a
output 30 y
assign y a
endmodule

47
Reduction Operators

Apply a single logic function to multiple-bit
inputs
module and8(a, y)
input 70 a
output y
assign y a
endmodule

48
Conditional Operators

Like C/C/Java Conditional Operator
module mux2(d0, d1, s, y)
input 30 d0, d1
input s
output 30 y
assign y s ? d1 d0// if s1, yd1, else
yd0
endmodule

49
More Operators

Equivalent to C/C/Java Operators
Arithmetic - /
Comparison ! lt lt gt gt
Shifting ltlt gtgt
Example
module adder(a, b, y)
input 310 a, b
output 310 y
assign y a b
endmodule
Small expressions can create big hardware!

50
Bit Manipulation Concatenation

is the concatenation operator
module adder(a, b, y, cout)
input 310 a, b
output 310 y
output cout
assign cout,y a b
endmodule

51
Bit Manipulation Replication

n pattern replicates a pattern n times
module signextend(a, y)
input 150 a
output 310 y
assign y 16a15, a150
endmodule

52
Internal Signals

Declared using the wire keyword
module fulladder(a, b, cin, s, cout)
input a, b, cin
output s, cout
wire prop, gen
assign prop a b
assign gen a b
assign s prop cin
assign cout gen (cin prop)
endmodule

53
Some Language Details

Syntax - See Quick Reference Card
Major elements of language
Lexical Elements (tokens and token
separators)
Data Types and Values
Operators and Precedence
Syntax of module declarations

54
Verilog Lexical Elements

Whitespace - ignored except as token separators
blank spaces
tabs
newlines
Comments
Single-line comments //
Multi-line comments / /
Operators- unary, binary, ternary
Unary a b
Binary a b c
Ternary a (b lt c) ? b c

55
Verilog Numbers

Sized numbers ltsizegt'ltbase formatgtltnumbergt
ltsizegt - decimal number specifying number of bits
ltbase formatgt - base of number
decimal 'd or 'D
hex 'h or 'H
binary b or B
ltnumbergt - consecutive digits
normal digits 0, 1, , 9 (if appropriate for
base)
hex digits a, b, c, d, e, f
x "unknown" digit
z "high-impedance" digit
Examples
4b1111 12h7af 16d255

56
Verilog Numbers (cont'd)

Unsized numbers
Decimal numbers appearing as constants (236, 5,
15, etc.)
Bitwidth is simulator-dependent (usually 32 bits)
Negative numbers
sized numbers '-' before size -8'd127 -3'b111
unsized numbers '-' before first digit -233
As in VHDL, underline '_' can be used as a
"spacer
12'b00010_1010_011 is same as
12'b000101010011

57
Verilog Strings

Anything in quotes is a string "This is a
string" "a / b"
Strings must be on a single line
Treated as a sequence of 1-byte ASCII values
Special characters - C-like (\)

58
Verilog Identifiers

Starting character alphabetic or '_'
Following characters alpha, numeric, or '_'
Examples george _paul
"Escaped" identifiers
start with backslash
follow with any non-whitespace ASCII
end with whitespace character
Examples \212net \xyzzy \foo
Special notes
Identifiers are case sensitive
Identifiers may not be reserved words

59
Verilog Reserved Words

always and assign begin buf bufif0 bufif1 case
casex casez cmos deassign default defparam disabl
e edge
else end endcase endfunction endmodule
endprimitive endspecify endtable endtask event for
force forever fork function highz0 highz1 if ifnon
e
initial inout input integer join large macromodule
medium module nand negedge nmos nor not
notif0 notif or output parameter pmos
posedge primitive pull0 pull1 pulldown pullup rcmo
s
real realtime reg release repeat rnmos rpmos rtran
rtranif0 rtranif1 scalared small specify specparam
strong0
strong1 supply0 supply1 table task time tran trani
f0
tranif1 tri tri0 tri1 triand trior trireg vectored
wait wand weak0 weak1 while wire wor xnor
xor

60
Verilog Data Types

Nets - connections between modules
input, output ports
wires - internal signals
Other types wand, wor, trior, trireg (ignore for
now)
Advanced Data Types (more later)
Vectors - multiple bit wires, registers, etc.
reg - Variables that are assigned values
Arrays and Memories
Parameters

61
Operators and Precedence

Override with parentheses () when needed

62
Verilog Module Declaration

Describes the external interface of a single
module
Name
Ports - inputs and outputs
General Syntax
module modulename ( port1, port2, ... )
port1 direction declaration
port2 direction declaration
reg declarations
module body - parallel statements
endmodule // note no semicolon () here!

63
Verilog Body Declaration - Parallel Statements

Parallel statements describe concurrent behavior
(i.e., statements which execute in parallel)
Types of Parallel Statements
assign - used to specify simple combinational
logic
always - used to specify repeating behavior for
combinational or sequential logic
initial - used to specify startup behavior (not
supported in synthesis)
module instantiation - used for structure
and other features well talk about later

64
Combinational Modeling with always