Low power design: Insert delays to eliminate glitches

1
Low power design Insert delays to eliminate
glitches

• Yijing Chen
• Dec.6, 2005
• Auburn university

2
Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

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Dynamic Power

• Each transition of a gate consumes CV2/2.
• Methods of power saving
• Minimize load capacitances
• Transistor sizing
• Library-based gate selection
• Reduce transitions
• Logic design
• Glitch reduction

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Glitch Power Reduction

• Design a digital circuit for minimum transient
  energy consumption by eliminating hazards

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Theorem

• For correct operation with minimum energy
  consumption, a Boolean gate must produce no more
  than one event per transition.

Output logic state changes One transition is
necessary
Output logic state unchanged No transition is
necessary
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Balanced Delay Method

• All input events arrive simultaneously
• Overall circuit delay not increased
• Delay buffers may have to be inserted

4?
1
1
1
1
1
3
1
1
1
1
1
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Cell of multiplier
Static power 320.0184pW Average power
107.1806uW
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Simulation result of cell
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Delay is added in the cell
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Simulation result for delay is added
Static power 568.6279pW average power
144.8164uW
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4x4 multiplier
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4x4 multiplier simulation result
Static power 4.7694nW , average power1.8339mW
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Critical path
j
i
Cell Mij has the longest delay path length
of 2ij1
14
Delay balanced multiplier cell
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Modified 4X4 multiplier
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Conclusion

• The delay-balancing technique can be used on all
  types of parallel array multipliers such as
  Booths multiplier and Wallace Tree multiplier.
• Achieves power reduction of 36 on a parallel
  array multiplier

17
Reference

• Dr. AGRAWALs Elec 6970 slides
• Gary Yeap (motorola) , Practical low power
  digital VLSI design, Kiuwer Academic publishers,
  1998.