ECE%20331%20

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ECE 331 Digital System Design

• Constraints in Logic Circuit Design
• (Lecture 14)

The slides included herein were taken from the
materials accompanying Fundamentals of Logic
Design, 6th Edition, by Roth and Kinney, and
were used with permission from Cengage Learning.
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Material to be covered

• Supplemental
• Chapter 8 Sections 1 5

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Power Consumption
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Power Consumption

• Each integrated circuit (IC) consumes power
• Power consumption can be divided into two parts
• Static power consumption (PS)
• Dynamic power consumption (PD)
• Total power consumption (PT) can then be
  determined as
• PT PS PD

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Static Power Consumption

• PS VCC ICC
• VCC supply voltage
• ICC supply current
• ICC and VCC are specified in the datasheet for
  the integrated circuit (IC).
• For TTL devices, PS is significant.
• For CMOS devices, PS is very small (0 W).

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Example 74LS08
VCC
ICCH, ICCL
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Example 74LS32
VCC
ICCH, ICCL
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Example 74HC32
VCC
ICC
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Example Static Power Consumption
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Example Static Power Consumption

• The static power consumption is a function of the
  duty cycle.
• duty cycle percentage of time in the high state
  
• PS PS_high thigh PS_low tlow
• where thigh time in the high state
• and tlow time in the low state
• Assume a 50 duty cycle
• PS PS_high 0.5 PS_low 0.5
• Assume a 60 duty cycle
• PS PS_high 0.6 PS_low 0.4

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Example Static Power Consumption
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Time Delay
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Time Delay

• A standard logic gate does not respond to a
  change in its input(s) instantaneously.
• There is, instead, a finite delay between a
  change in the input and a change in the output.
• The propagation delay of a standard logic gate is
  defined for two cases
• tPLH delay for output to change from low to
  high
• tPHL delay for output to change from high to low

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Time Delay
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Time Delay

• The time delay (both tPLH and tPLH) for a logic
  gate is specified in its datasheet.
• The time delay is also known as the
• gate delay
• propagation delay of the logic gate.

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Example 74LS08
tPHL, tPLH
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Example 74LS32
tPHL, tPLH
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Example 74HC32
tPHL, tPLH
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Time Delay

• The time delay of individual logic gates can be
  used to determine the overall propagation delay
  of a logic circuit.
• The propagation delay of a logic circuit can be
  used to define
• When the output of the logic circuit is valid.
• The maximum speed of the combinational logic
  circuit.
• The maximum frequency of the sequential logic
  circuit.

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Timing Analysis

• A simple timing analysis can be performed on a
  logic circuit assuming that
• only one input transitions at a time
• The time delay between the transition on the
  input and the transition on the output can be
  determined as follows
• identify the path between the input and output
• sum the gate delays of all gates in the path

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Timing Analysis

• However,
• Some logic circuits have more than one path
  between an input and the output.
• In some logic circuits, multiple inputs
  transition at the same time.
• The simple timing analysis will not work.
• Instead, perform a more conservative timing
  analysis using the
• Sum of Worst Cases (SWC) Analysis method

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Timing Analysis SWC

• Identify all input-output paths (i.e. delay
  paths)
• Using the datasheet, select the worst-case gate
  delay for each logic gate.
• Select maximum of tPLH and tPHL
• Calculate the worst-case delay for each path
• Sum the gate delays of the gates in the path
• Select the worst case
• The maximum propagation delay for the circuit

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Timing Analysis SWC

• Example
• Using the SWC analysis method, determine the
  maximum propagation delay for the Exclusive-OR
  (XOR) Logic Circuit.

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Example SWC
tPLH (ns) tPLH (ns) tPLH (ns) tPHL (ns) tPHL (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
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Example SWC
tPD 26.1 ns
tPLH (ns) tPLH (ns) tPLH (ns) tPHL (ns) tPHL (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
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Example SWC
tPD 27.3 ns
tPLH (ns) tPLH (ns) tPLH (ns) tPHL (ns) tPHL (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
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Example SWC
tPD 32.1 ns
tPLH (ns) tPLH (ns) tPLH (ns) tPHL (ns) tPHL (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
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Example SWC
A
74LS08
B
74F04
F
74F32
74LS04
74F08
tPD 12.3 ns
tPLH (ns) tPLH (ns) tPLH (ns) tPHL (ns) tPHL (ns) tPHL (ns)
min typ max min typ max
74LS04 0 9 15 0 10 14
74F04 2.4 3.7 6.0 1.5 3.2 5.4
74LS08 0 8 18 0 10 20
74F08 2.4 3.7 6.2 2.0 3.2 5.3
74F32 2.4 3.7 6.1 1.8 3.2 5.5
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Example SWC
Input Output Delay (ns)
A (1) F 26.1
A (2) F 27.3
B (1) F 32.1
B (2) F 12.3
Worst Case Propagation Delay 32.1 ns
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Transient Behavior
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Hazards
When the input to a combinational logic circuit
changes, unwanted switching transients may appear
on the output. These transients occur when
different paths from input to output have
different propagation delays.
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Hazards
transient
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Static 1-Hazards

• When analyzing combinational logic circuits for
  hazards we will consider the case where only one
  input changes at a time.
• Under this condition, a static 1-hazard occurs
  when the input change causes one product term (in
  a SOP expression) to transition from 1 to 0 and
  another product term to transition from 0 to 1.
• Both product terms can be transiently 0,
  resulting in the static 1-hazard.

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Detecting Static 1-Hazards
We can detect hazards in a two-level AND-OR
circuit using the following procedure

1. Write down the sum-of-products expression for the
   circuit.
2. Plot each term on the K-map and circle it.
3. If any two adjacent 1's are not covered by the
   same circle, a 1-hazard exists for the transition
   between the two 1's. For an n-variable map, this
   transition occurs when one variable changes and
   the other n 1 variables are held constant.

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Detecting Static 1-Hazards
A 1 C 1
gate delay 10ns
B 1 ? 0 at 20ns
Static 1-Hazard
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Removing Static 1-Hazards
redundant, but necessary to remove hazard
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Static 0-Hazards

• Again, consider the case where only one input
  changes at a time
• Under this condition, a static 0-hazard occurs
  when the input change causes one sum term (in a
  POS expression) to transition from 0 to 1 and
  another sum term to transition from 1 to 0.
• Both sum terms can be transiently 1, resulting in
  the static 0-hazard.

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Detecting Static 0-Hazards
We can detect hazards in a two-level OR-AND
circuit using the following procedure

1. Write down the product-of-sums expression for the
   circuit.
2. Plot each sum term on the map and loop the zeros.
3. If any two adjacent 0's are not covered by the
   same loop, a 0-hazard exists for the transition
   between the two 0's. For an n-variable map, this
   transition occurs when one variable changes and
   the other n 1 variables are held constant.

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Detecting Static 0-Hazards
A 0 B 1 D 0
Static 0-Hazard
C 0 ? 1 at 5ns
AND/OR delay 5ns NOT delay 3ns
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Removing Static 0-Hazards
How many redundant gates are necessary to remove
the 0-hazards?
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Hazards

• Exercise
• Design a hazard-free combinational logic circuit
  to implement the following logic function
• F(A,B,C) A'.C' A.D B.C.D'

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Hazards

• Exercise
• Design a hazard-free combinational logic circuit
  to implement the following logic function
• F(A,B,C) (A'C').(AD).(BCD')

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Hazards

• Two-level AND-OR circuits (SOP) cannot have
  Static 0-Hazards.
• Why?
• Two-level OR-AND circuits (POS) cannot have
  Static 1-Hazards.
• Why?

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Questions?