Prsentation PowerPoint

1
VFE PCB
Status schedule of production
Christophe de La Taille, Julien Fleury, Gisèle
Martin-Chassard
Presented by Julien Fleury
2
Plan
Measurement result on FLC_PHY1 - Linearity
dynamic range - Pedestal dispersion noise

• Introducing the new FLC_PHY2 front end chip
• General presentation
• The new charge preamplifier
• The new shaper
• The new track hold

• Schedule of the front-end electronic group
• Front-end chip PCB schedule

3
Meas. Results linearity dyn. range

• Linearity measured
• Preamplifier linearity .. 0.1
• Direct shaper output linearity. 0.3
• Multiplexed output . 0.2

• Dynamic range
• Measured .. 3.5 pC (550 MIP)
• Simulated 4.2 pC (650 MIP)

4
Meas. Results Pedestal disp noise

• Noise measured
• Cline ... 80pF
• Peaking time 200 ns
• Measured noise 2200e-

Pedestal dispersion

• Pedestal dispersion measured
• Average . -3.129V
• Standard deviation. 5mV
• Excursion . 17mV

Settling time
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Meas. Results Conclusion
FLC_PHY1 reachs expectation for physics prototype
Noise
Linearity
Dyn.range
6
New FLC_PHY2 General presentation
FLC_PHY1
FLC_PHY2
Pin-Pin compatibility

• Preamp ? 1 gain (1.5pF)
• Low noise (2200e-)
• Shaper ? Mono gain unipolar
• track hold ? Unipolar

• Preamp ? 16 gains (0.2, 0.4, 0.8, 1.6pF
  switchable)
• Lower noise (input trans improved)
• Shaper ? bigain differential
• track hold ? differential

7
New FLC_PHY2 charge preamp
Characteristics

• 4 switchable feedback capa
• Max out from 80?1300 MIP
• input PMOS size increased
• ?noise reduced

• Hardware configuration
• No modification of the read-out interface
• Gain switches driven on VFE board

8
New FLC_PHY2 shaper

• Filter structure stays (CRRC)
• High gain amplifier is replaced by an OP AMP
• ?Differential structure makes the pedestal
  dispertion lower
• The OP AMP have been designed and layouted in
  LAL (used in OPERA slow shaper)

New version
Old version
9
New FLC_PHY2 shaper

• Peaking time is 200ns on both gain
• High-gain shapers can be shut down by switching
  off their biases
• Two different output for low gain and high gain
• Interface compatibility with the read out is kept
• New interface not written at this point

10
New FLC_PHY2 track hold

• Including a Widlar structure (differential) to
  reduce pedestal dispersion
• Common collector buffer structure is kept for
  safety
• Memory capacitance is increased from 1 to 2pF

11
New FLC_PHY2 Conclusion

• Pin to pin compatibility with FLC_PHY1 ? to
  simplify PCB design
• Read out interface compatibility with FLC_PHY1
• ? RD on the front end chip has no influence on
  PCB and RO development

12
Schedule Front end chip PCB
PCB
Design
Fab
Test
Production
FLC_PHY1
Test
Choice
Standby
Production
FLC_PHY2
Design
Foundry
Test
November
April, 7th
June, 23rd
Sept.
GOAL Be ready for cosmics test in february
2004 ? Build VFE boards in January 2004