COMP541 Datapaths I

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COMP541Datapaths I

• Montek Singh
• Mar 8, 2007

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Topics

• Over next 2/3 classes datapaths
• Basic register operations
• Book sections 7-2 to 7-6 and 7-8
• Computer datapaths
• First part of Chapter 10

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Parts of CPUs

• Datapath
• The registers and logic to perform operations on
  them
• Control unit
• Generates signals to control datapath

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Memory and I/O

• Are connected to the data/control in and out
  lines
• Example register to memory ops

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Microoperations

• Basic operations of the datapath
• Example moving data from one register to another
• Not necessarily microprogrammed control
• Just a description of operations
• Microoperation expected to complete in one clock
• Register transfer notation, next

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Register Transfer Language (RTL)

• Registers named in uppercase
• PC, IR (instruction), R3
• Little endian

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RT

• Transfer from R1 to R2
• R2 ? R1
• R2 is destination
• R1 is source
• Conditional
• If(K1 1) then (R2 ? R1)
• K1 R2 ? R1 as a shorter form

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Transfer

• Transfer at the clock edge
• When K1 is high
• n bits wide

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Symbols

• Note memory transfers

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Syntax not Verilog (but similar)
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Types of Microoperations

• Transfer have just looked at
• Arithmetic
• Logic
• Shift

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Arithmetic

• Basic ops (not multiply, divide)
• R0 ? R1 R2
• Subtraction by 2s complement

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Notation is Shorthand for Hardware

• Consider
• and
• Note overflowand carry registers

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Logic Microoperations

• OR notation a little confusing
• shows two types of syntax for ORs

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Shift Microoperations

• Here just the basic one-bit shifts
• Bit falls off the end, zero shifted in

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Multiplexer-Based Transfers

• Consider
• Which can also be expressed as
• Block diagram next

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Multiplexer Block Diagram

• Detailed block diagram next

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Detailed

• Simpler version is easier to follow and to derive

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Bus-Based Transfers

• How about when there are lots of registers?
• Beyond a certain point muxes become unwieldy
• Can use buses and send data over common set of
  wires

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Simple Cases

• One mux
• One output bus

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Transfers

• Cant be as general
• Only single source
• About ½ the hardware

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Three-State Bus

• Remember three-state drivers allow having
  multiple outputs share wire
• Have to control so only one is asserted
• Example next

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Same Example with 3-State

• One R output
• Enable controls
• Load controls which latches
• Fewer wires
• Especially important outside chip

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Memory Transfers

• Usually one or more buses associated with memory
• Address
• Data
• Note that memory can be slower, so may have to
  use complex timing
• Address on one clock cycle
• Data latched at later clock cycle

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Datapath

• Blue signals generated by control
• AB buses to ALU
• B can be constant from memory
• Can also send addr and data

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R1?R2R3

• Signals
• Load enable
• A, B select
• MB Select
• MF Select
• G Select
• Destination (D)
• What about timing?

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Timing

• All can occur in one clock, but
• Signals must be available in time to propagate
  through muxes, ALU and
• Be at R inputs by next posedge
• Go back and look at path

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Next

• Look at specific MIPS design
• Next time
• Continue design review of ALU
• Look at shifter