COMP541 State Machines 2 Registers and Counters

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COMP541State Machines 2Registers and Counters

• Montek Singh
• Feb 8, 2007

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Topics

• Lab preview
• State machine specification styles
• Functional State tables/diagrams/graphs
• Structural Boolean equations
• Behavioral Verilog
• Building blocks registers and counters

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Lab Preview

• Digital lock
• Recognize sequence of four 4-bit input values
• Input
• Use 4 DIP switches on the board
• Output
• Indicate yes/no on LED display
• Concepts learned
• State machine specification
• State machine synthesis
• Generating/measuring time intervals
• Switch button debouncing

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Time intervals

• module cntr(output out, input clk)
• reg 310 count
• always _at_ (posedge clk)
• count lt count 1
• assign out count22
• endmodule

What does this do?
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Button and Debouncing

• Button normally high
• Mechanical switches can bounce
• Go 1 and 0 a number of times
• Well want to
• Debounce Any ideas?
• Synchronize with clock

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Flip-Flop for pushbutton

• module button_test( output q, input btn, input
  clk )
• reg q
• always _at_ (posedge clk)
• begin
• if(btn 1)
• q lt 1
• else
• q lt 0
• end
• endmodule

What does this do?
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Simple Module to Begin With

• module led_on(output s6, input button, input
  clk)
• wire clkb //opt
• cntr C1(clkb, clk)
• button_test B1(s6, button, clkb)
• endmodule

• clk to board clock, P88
• button to pushbutton, P93
• Why button?
• s6 to one of LED segments

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Things to Think About

• Can I press button and not light LED?
• What happens if I hold button down for a long
  time?
• What effect will changing period of clkb have?
• On LED
• On button debouncing
• What does it mean to press the button?
• Think carefully about this

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Revisit sequence detector example

• Design a state machine to detect the pattern 1101
• In last class We developed state graph for it
• Today Learn how to code this in Verilog

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Verilog Case Statement

• Similar to sequence of if/then/else
• case (expression)
• case statements
• other case statements
• default statements // optional
• endcase
• Example in a moment

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Parameter defines constant

• module seq_rec_v(CLK, RESET, X, Z)
• input CLK, RESET, X
• output Z
• reg 10 state, next_state
• parameter A 2'b00, B 2'b01,
• C 2 'b10, D 2'b11

Notice that weve assigned codes to the states
more later
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Next State specification

• always _at_(X or state)
• begin
• case (state)
• A if (X 1)
• next_state lt B
• else
• next_state lt A
• B if(X) next_state lt Celse next_state lt
  A
• C if(X) next_state lt Celse next_state lt
  D
• D if(X) next_state lt Belse next_state lt
  A
• endcase
• end

The last 3 cases do same thing. Just compact
style.
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On Reset or CLK

• always _at_(posedge CLK or posedge RESET)
• begin
• if (RESET 1)
• state lt A
• else
• state lt next_state
• end

Notice that state only gets updated on ve edge
of clock (or on reset)
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Output

• always _at_(X or state)
• begin
• case(state)
• A Z lt 0
• B Z lt 0
• C Z lt 0
• D Z lt X ? 1 0
• endcase
• end

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Pitfall Beware of Unexpected Latches!

• You can easily specify latches unexpectedly
• Hangover from programming in C!
• always will try to synthesize FF
• if (select) out lt A
• if (!select) out lt B
• FF added to save old value if condition is false
• To avoid extra FF, cover all possibilities
• if (select) out lt A
• else out lt B

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Comment on Book Code

• Could shorten
• Dont need next_state, for example
• Can just set state on clock
• Note that the two are a little different in
  function
• Dont need three always clauses
• Although its easier to have combinational code
  to set output be separate
• Template helps synthesizer
• Check to see whether your state machines were
  recognized

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Registers and Counters Definitions

• Register a set of flip-flops
• May include extensive logic to control state
  transition
• May allow shifting
• register also refers to fast memory for storing
  data in a computer
• Counter
• Register that goes through sequence of states as
  it is clocked

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Simple Register

• Store D
• On posedge of Clock
• Clear signal normally high
• Power-up reset
• Symbol

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Clocking

• Typically dont want to load every clock
• Can gate the clock
• But added clock skew is a problem

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Enable

• If load H, then D is gated through
• Otherwise, Q is fed back
• Keep same value
• No clock gating

• Did this because D FF doesnt have a no change
  behavior

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Counters

• Counter is a register has state
• Also goes through sequence of states counts
  on clock or other pulses
• Binary counter
• Counts through binary sequence
• n bit counter counts from 0 to 2n

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Ripple Counter

• Simple
• So Q will alternate 1 and 0
• Why called ripple counter?

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Synchronous Counters

• Ripple counter is easy
• Asynchronous nature may cause problems, though
• Delay!
• Synchronous counter most common

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Synchronous Counter

• Does have sequence of gates
• Delay again

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Parallel Design

• Now constant delay
• Can gang these to make long serial-parallel
  counter

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Verilog Counter (simple)

• module count (CLK, EN, Q)
• input CLK, EN
• output 30 Q
• reg 30 Q
• always_at_(posedge CLK)
• begin
• if (EN)
• Q lt Q 4'b0001
• end
• endmodule

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Verilog Counter (from book)

• module count_4_r_v (CLK, RESET, EN, Q, CO)
• input CLK, RESET, EN
• output 30 Q
• output CO
• reg 30 Q
• assign CO (count 4'b1111 EN 1b1) ? 1
  0
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• Q lt 4'b0000
• else if (EN)
• Q lt Q 4'b0001
• end
• endmodule

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Arbitrary Count

• One more type of counter is useful
• Count an arbitrary sequence
• Maybe you need a sequence of states

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Circuit and State Diagram
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Shift Registers

• Capability to shift bits
• In one or both directions
• Why?
• Part of standard CPU instruction set
• Cheap multiplication
• Serial communications
• Just a chain of flip-flops

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Simple 4-Bit Shift Register

• Clocked in common
• Just serial in and serial out
• Is this a FIFO?

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Parallel Load

• Can provide parallel outputs from flip-flops
• And also parallel inputs

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Schematic
Detail Next
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Detail
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Why is this useful?

• Basis for serial communications
• Keyboard
• Serial port
• Initially to connect to terminals
• Now mainly for modem
• USB
• Firewire

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Example
Why do this? Maybe these are far apart
Could shift data in, or parallel load
Whats on wire at each clock?
Clocked 4 times
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Table Showing Shift
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Serial vs. Parallel Transfer

• Parallel transfer over as many wires as word
  (for example)
• Serial transfer over a single wire
• Trade time for wires
• Takes n times longer

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Bidirectional Shift Register

• Shift either way
• Now we have following possible inputs
• Parallel load
• Shift from left
• Shift from right
• Also no change
• Schematic next

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Schematic
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Verilog for Shift Register

• module srg_4_r (CLK, SI, Q, SO)
• input CLK, SI
• output 30 Q
• output SO
• reg 30 Q
• assign SO Q3
• always_at_(posedge CLK)
• begin
• Q lt Q20, SI
• end
• endmodule

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Next Time

• How to generate a VGA signal
• More on state machines

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Optional Example One Shot

• Help me analyze this one
• What does it do?