COMP541 Sequencing

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COMP541Sequencing III(Sequencing a Computer)

• Montek Singh
• April 9, 2007

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Test 2

• On April 17
• Covers
• Memories
• Arithmetic
• Datapaths
• Sequencing

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Design Reviews Last Week of Classes

• Individual meetings during class time next week
  (and maybe one more day)
• 20 minutes
• Please prepare a presentation
• Not necessarily a PPT, but dont make up your
  description on the fly

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Chapter 10-7

• Simple computer architecture
• Not unlike MIPS, except 16 bits
• Single-cycle hardwired control
• Multicycle microprogrammed control

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Instruction Formats

• Register-type instructions
• Only 8 registers (3 bits)

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Immediate

• Only 3 bits for the immediate value (Op)
• Mostly useful for typical increments/decrement
• Or just as an example

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Branching

• PC relative branching
• The 6 bits are sign extended to 16
• Opcode might specify branch on zero, if register
  SA is zero

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Example Instructions
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Contrast to Microoperations

• Although appear similar, theyre not
• Computer instructions fetched using PC
• Branching much more general
• Decoding of computer instructions usually more
  complex

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Resources

• Book implies Harvard architecture
• Separate I and D
• They treat I memory as ROM
• Asynchronous

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Single-Cycle Control

• Datapath is same as example we used in datapath
  topic
• Next slide shows for review
• First look at overall control
• Then look at instruction decoder

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Datapath Control Word
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Arch
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Instruction Decoder

• Many lines (the three regs) need no logic
• RISC Style
• Architecture tailored so parts of inst.
  correspond to control lines

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Control

• Not much more to say
• Simple, partly because decoding so
  straightforward
• Drawbacks
• Some instructions, like multi-cycle shifts, cant
  be implemented w/o complex datapath
• Two memories (essentially a ROM and an async data
  memory)
• Two cycles needed to use one memory
• Biggest problem is delay

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Delay in Single-Cycle Control

• Worst case delay with reasonable components
• Say, total 17ns
• Could only clock at about 50 MHz
• Pipelining is a solution
• First lets look at multi-cycle control

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Multi-Cycle Hardwired Control

• Goals
• Support more complex instructions
• Use single memory
• Not necessarily coupled with multi-cycle

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Arch
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Instruction Register

• IL load signal for IR
• PS, for PC control
• Hold value multiple cycles, increment, load, etc.

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Single Memory

• PC addresses memory
• Mux M gates address
• MM signal to select program/data address
• Inst. stored in IR

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Added Temporary Regs

• Now 16x16
• 8 not visible to user
• New signals to address the registers

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Sequence Control
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Control Word
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Control Design

• Not hard to specify state diagram
• Derived from definition of ISA
• Hard to design logic manually
• If didnt have logic synthesis, would probably
  use microprogramming

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Two-Cycle Instructions

• Simplest instructions have 2 cycles
• Fetch (instruction)
• Execute
• This is minimum necessary
• They assume async memory
• Dont need extra clock cycles

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Basic Inst.
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Branch

• Test and modify PC

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Next Step

• Make a table or write Verilog from ASM diagram
  and instruction descriptions
• Tedious, but not hard
• Same as youve done, with more details
• State machine easy for these instructions

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Table from ISA and ASM
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Load Register Indirect

• Three cycles
• Temporary register used

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Shift

• Shift right/left multiple
• RSA to be shifted
• First tested for 0
• R9 loaded with shift length

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Multi-Cycle Table
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Summary multi-cycle

• Multi-cycle computer enables more complex
  instructions
• May also be faster
• Well also briefly look at pipelined computers
  more parallelism but more complex control

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Limits to Clock Period

• Conventional datapath
• 12 ns delay, so maximum is 83 MHz clock
• Maybe have even tighter constraints due to
  control logic

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Pipelining

• Break datapath into stages
• Add registers between stages
• Like production line book uses car wash example
• Wash, rinse, dry

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Latency vs Throughput

• Latency, the amount of time it takes to execute
  an instruction, does not improve
• In fact, typically increases
• Throughput, the number of instructions executed
  per second, increases
• By almost the number of pipeline stages

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Expected Performance

• Longest stage is 5ns
• So clock can be 200 MHz
• Not 3 x 83 MHz. Why?
• Latency is 15ns
• Also extra hardware

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Datapath

• 3 Stages
• Operand Fetch
• Execute
• Write Back
• Note that WB register is the register file (same
  as at top)

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Pipelined Execution

• Note pipeline fill and empty
• Efficiency is not 100
• Important to not stall pipeline