COMP541 Sequential Circuits

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COMP541Sequential Circuits

• Montek Singh
• Feb 1, 2007

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Administrative

• Advance Notice
• Test Week of Feb 19-23
• Covers material through Thursday 2/15
• Short review session on 2/15 in class

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Topics

• Sequential Circuits
• Latches
• Flip Flops
• Verilog for sequential design

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Sequential Circuits

• State of system is info stored
• That, and inputs, determine outputs

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Types of Sequential Circuits

• Synchronous
• State changes synchronized by one or more clocks
• Asynchronous
• Changes occur independently

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Clocking of Synchronous

• Changes enabled by clock

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Comparison

• Synchronous
• Easier to analyze because can factor out gate
  delays
• Set clock so changes occur before next clock
  pulse
• Asynchronous
• Potentially faster
• Harder to analyze (more subtle, but more
  powerful!)
• Most of my research!
• Will look mostly at synchronous

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Basic Storage

• Apply low or high for longer than tpd
• Feedback will hold value

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SR (set-reset) Latches

• Basic storage made from gates

• S R both 0 in resting state
• Have to keep both from 1 at same time

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Operation
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Latch

• Similar made from NANDs

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Add Control Input

• Gates when state can change

• Is there latch w/ no illegal state?

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D-type Latch

• No illegal state

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Transparency of latches

• As long as C (the control ) is high, state can
  change
• This is called transparency
• Whats problem with that?

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Effects of Transparency

• Output of latch may feed back
• May cause further state changes
• Behavior depends on actual gate delays
• Want to change latch state only once
• Behavior should depend only on logical values

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Solution to Transparency Flip-Flops

• Flip-Flops
• Ensure output changes only once per clock cycle
• Two commonly-used types of flip-flops
• Master-Slave
• Use a sequence of two latches
• Edge-Triggered
• Implementation very different from latches

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1. Master-Slave Flip-Flop

• Either Master or Slave is enabled, not both

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Timing Diagram

• Trace the behavior
• Note illegal state
• Is it transparent?

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Have We Fixed the Problem?

• Output no longer transparent
• Combinational circuit can use last values
• New inputs appear at latches
• Not sent to output until clock low
• But changes at input of FF when clock high do
  trigger next state
• Is this a problem?
• As clock faster, more problems
• Have to guarantee circuit settles while clock low

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2. Edge-Triggered Flip-Flops

• New state latched on clock transition
• Low-to-high or high-to-low
• ve edge-triggered, -ve edge-triggered
• Also dual-edge-triggered
• Changes when clock high are ignored
• Note Master-Slave sometimes called pulse
  triggered

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D-Type Edge-Triggered

• Is this ve or ve edge-triggered?

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Standard Symbols Latches

• Circle at input indicates negation

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Symbols Master-Slave

• Inverted L indicates postponed output
• Circle indicates whether enable is positive or
  negative
• JK like an SR flip-flop, but
• If JK1, output is toggled
• Can make a toggle flip-flop (T flip-flop) from a
  JK

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Symbols Edge-Triggered

• Arrow indicates edge trigger

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Direct Inputs

• Use to force Set/Reset independent of clock
• Direct set or preset
• Direct reset or clear
• Often used for power-up reset

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Flip-Flop Timing

• Setup time time that D must be steady before
  clock edge
• Hold time time that D must continue to be
  steady after clock edge

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Propagation Delay

• Propagation delay time after edge until output
  becomes available

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Clock Pulse Requirements

• Determine the max clock frequency

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In Passing Clock Gating and Skew

• Can gate or freeze clocks
• to keep any FF from changing states
• Can help reduce power consumption
• However, can cause clock skew
• Clock edges at different times on different FFs
• Clock skew also caused by wire lengths over chip

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Next Time

• State Diagrams
• Sec. 6-4 and 6-5
• Pages 258-275
• Skip last part of 6-5
• Verilog to describe state machines