COMP541 More on State Machines and Video Scanout

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COMP541More on State Machinesand Video Scanout

• Montek Singh
• Feb 13, 2007

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Outline

• Look at Verilog coding practices
• Types of state machines
• How to generate video signal

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Good Verilog Practices

• Best to use single clock for all FFs
• Make all signals synchronous
• Avoids weird and frustrating problems
• Multiple modules
• Tested individually
• One module per file
• Just to make it easier to follow and test

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Assignment (of signals)

• Continuous
• Procedural
• Note there are two uses for always
• To generate FFs and latches (plus gates)
• Combinational only
• Latter does not introduce unnecessary FFs
• If synthesizer detects all possibilities covered
  (i.e. no state)
• Look at the synthesizer log

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Procedural Assignment 1

• module C2(output reg C 0, input A, input B)
• always _at_ (A or B)
• case (A, B)
• 2'b11 C lt 1
• default C lt 0
• endcase
• endmodule
• Schematic next page

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Schematic

• LUT is a look-up table
• Double clicking it shows

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Procedural Assignment 2

• module C1(output reg C 0, input A, input B)
• always _at_ (A or B)
• begin
• if(A 1 B 1)
• C lt 1
• end
• endmodule
• Synthesizer now says
• WARNINGXst737 - Found 1-bit latch for signal
  ltCgt.
• WARNINGXst1426 - The value init of the
  FF/Latch C hinder the constant cleaning in the
  block C1.

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Schematic

• LDE is latch
• Small box is clock driver

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In fact

• If I change the INIT of C like it says
• output reg C 1
• Synthesizer says
• INFOXst1304 - Contents of register ltCgt in
  unit ltC1gt never changes during circuit operation.
  The register is replaced by logic.

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Schematic

• module C1(output reg C 1, input A, input B)
• always _at_ (A or B)
• begin
• if(A 1 B 1)
• C lt 1
• end
• endmodule

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Types of state machine

• Try to explain what synthesizer is doing
• Read the messages on the console

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Example State Machine

• From XST manual
• Small error

x1
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One Always Block (simplified see handout)

• always_at_(posedge clk) begin
• case (state)
• s1 if (x1 1'b1) begin
• state lt s2 outp lt 1'b1
• end
• else begin
• state lt s3 outp lt 1'b0
• end
• s2 begin
• state lt s4 outp lt
  1'b1
• end
• s3 begin
• state lt s4 outp lt
  1'b0
• end
• s4 begin
• state lt s1 outp lt
  1'b0
• end
• endcase
• end

x1
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Synthesis Output

• Synthesizing Unit ltv_fsm_1gt.
• Related source file is "v_fsm_1.v".
• Found finite state machine ltFSM_0gt for signal
  ltstategt.
• ----------------------------------------------
  -------------------------
• States 4
  
• Transitions 5
  
• Inputs 1
  
• Outputs 4
  
• Clock clk (rising_edge)
  
• Reset reset (positive)
  
• Reset type asynchronous
  
• Reset State 00
  
• Power Up State 00
  
• Encoding automatic
  
• Implementation LUT
  
• ----------------------------------------------
  -------------------------
• Found 1-bit register for signal ltoutpgt.
• Summary
• inferred 1 Finite State Machine(s).

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Split Output Off

• Separate always for outp

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Code (see handout for full)

• always _at_(posedge clk)
• case (state)
• s1 if (x1 1'b1)
• state lt s2
• else
• state lt s3
• s2 state lt s4
• s3 state lt s4
• s4 state lt s1
• endcase
• always _at_(state)
• case (state)
• s1 outp 1'b1
• s2 outp 1'b1
• s3 outp 1'b0
• s4 outp 1'b0
• endcase

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Synthesis (no latch)

• Synthesizing Unit ltv_fsm_2gt.
• Related source file is "v_fsm_2.v".
• Found finite state machine ltFSM_0gt for signal
  ltstategt.
• ----------------------------------------------
  -------------------------
• States 4
  
• Transitions 5
  
• Inputs 1
  
• Outputs 1
  
• Clock clk (rising_edge)
  
• Reset reset (positive)
  
• Reset type asynchronous
  
• Reset State 00
  
• Power Up State 00
  
• Encoding automatic
  
• Implementation LUT
  
• ----------------------------------------------
  -------------------------
• Summary
• inferred 1 Finite State Machine(s).
• Unit ltv_fsm_2gt synthesized.

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Textbook Uses 3 always Blocks
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Three always Blocks

• always _at_(posedge clk)
• begin
• state lt next_state
• end
• always _at_(state or x1)
• begin
• case (state)
• s1 if (x11'b1)
• next_state s2
• else
• next_state s3
• s2 next_state s4
• s3 next_state s4
• s4 next_state s1
• endcase
• end

• always _at_(state)
• begin
• case (state)
• s1 outp 1'b1
• s2 outp 1'b1
• s3 outp 1'b0
• s4 outp 1'b0
• endcase
• end

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Synthesis (again, no latch)

• Synthesizing Unit ltv_fsm_3gt.
• Related source file is "v_fsm_3.v".
• Found finite state machine ltFSM_0gt for signal
  ltstategt.
• ----------------------------------------------
  -------------------------
• States 4
  
• Transitions 5
  
• Inputs 1
  
• Outputs 1
  
• Clock clk (rising_edge)
  
• Reset reset (positive)
  
• Reset type asynchronous
  
• Reset State 00
  
• Power Up State 00
  
• Encoding automatic
  
• Implementation LUT
  
• ----------------------------------------------
  -------------------------
• Summary
• inferred 1 Finite State Machine(s).
• Unit ltv_fsm_3gt synthesized.

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My Preference

• The one with 2 always blocks
• Less prone to error than 1 always
• Easy to visualize the state transitions

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State Encoding

• So far weve used binary encoding
• Not necessarily best
• XST chooses one to minimize hardware
• Can change by right-clicking Synthesize-XST
• Possible encodings next slides

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Gray Code (synthesis output)

• 
  
• Advanced HDL Synthesis
  
• 
  
• Analyzing FSM ltFSM_0gt for best encoding.
• Optimizing FSM ltstategt on signal ltstate12gt
  with gray encoding.
• -------------------
• State Encoding
• -------------------
• 00 00
• 01 01
• 10 11
• 11 10
• -------------------

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One-Hot Encoding

• Optimizing FSM ltstategt on signal ltstate14gt
  with one-hot encoding.
• -------------------
• State Encoding
• -------------------
• 00 0001
• 01 0010
• 10 0100
• 11 1000
• -------------------

Hmmm, state register grew. Whats up?
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Safe Implementation Mode

• XST can add logic to your FSM implementation
  that will let your state machine recover from an
  invalid state. If during its execution, a state
  machine gets into an invalid state, the logic
  added by XST will bring it back to a known state,
  called a recovery state. This is known as Safe
  Implementation mode. from XST manual

Tuesdays counter
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How Do Monitors Work?

• Origin is TV, so lets look at that
• LCDs work on different principle, but all
  signaling still derived from TV of 1940s
• Relies on your brain to do two things
• Integrate over space
• Integrate over time

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Many Still Images

• Video (and movies) a series of stills
• If stills go fast enough your brain interprets as
  moving imagery
• 50-60 Hz or more to not see flicker
• In fact, even single still image displayed over
  time

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Cathode Ray Tube
From wikipedia http//en.wikipedia.org/wiki/Catho
de_ray_tube
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Deflection Coils
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Simple Scanning TV

• Electron beam scans across
• Turned off when
• Scanning back to the left (horizontal retrace)
• Scanning to the top (vertical retrace)

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Scanning

• TVs use interlacing
• Every other scan line is swept per field
• Two fields per frame (30Hz)
• Way to make movement less disturbing
• Computers use progressive scan
• Whole frame refreshed at once
• 60Hz or more, 72Hz looks better

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Color

• Three colors of phosphor
• Beams hit each
• Black beam off
• White all on

Picture is a bit misleading. Mask (or aperture
grill) ensures beams hit only correct color
phosphor.
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Aside

• Frustrated with Verilog
• See what to do to relieve stress
• http//science.howstuffworks.com/what-if-shoot-tv.
  htm
• Educational too

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VGA Signaling

• RGB and two synchronization pulses, horizontal
  and vertical

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VGA Timing

• You supply two pulses, hsync and vsync, that let
  the monitor lock onto timing
• One hsync per scan line
• One vsync per frame

Image from dell.com
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Horizontal Timing Terms

• hsync pulse
• Back porch (left side of display)
• Active Video
• Video should be blanked (not sent) at other times
• Front porch (right side)

Picture not accurate for our case just for
illustration. Video and HSYNC not on same wire
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Horizontal Timing
This diagram shows video as a digital signal.
Its not video is an analog level.

• 640 Horizontal Dots
• Horiz. Sync Polarity NEG
• Scanline time (A) 31.77 us
• Sync pulse length (B) 3.77 us
• Back porch (C) 1.89 us
• Active video (D) 25.17 us
• Front porch (E) 0.94 us

Image from http//www.epanorama.net/documents/pc/v
ga_timing.html
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Vertical Timing (note ms, not us)

• Vert. Sync Polarity NEG
• Vertical Frequency 60Hz
• Total frame time (O) 16.68 ms
• Sync length (P) 0.06 ms
• Back porch (Q) 1.02 ms
• Active video (R) 15.25 ms
• Front porch (S) 0.35 ms

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Timing as Pixels

• Easiest to derive all timing from single-pixel
  timing
• How long is a pixel?
• Active video / number of pixels
• 25.17 us / 640 39.32ns
• Conveniently close to 25 MHz just use that
• Actual VESA spec is 25.175 MHz

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Standards

• 640 x 480 (sometimes x 60Hz) is VGA
• Ill have spec sheets in lab
• You can try for 800x600 at 60 Hz (40 MHz exactly)
  
• or 800x600 at 72 Hz (50 MHz exactly)
• Note that some standards have vsync and hsync
  positive true, some negative true choose
  correct one

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Color Depth

• Voltage of each of RGB determines color
• 2-bit color here (4 shades)
• Turn all on for white

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What To Do Friday

• Make Verilog module to generate
• hsync, vsync, horizontal count, vertical count,
  and signal to indicate active video
• Use higher-level module to drive RGB using counts
  gated by active
• Just do something simple need to meet 25MHz
  constraint
• Later will use memory addressed by counts to make
  terminal

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What do you Need for VGA?

• Think first
• Need counter(s)?
• Will you need a state machine?
• Sketch out a design
• Block diagram
• Go over them individually in lab
• Keep in Mind
• Verilog has these operators
• , lt, gt, lt, gt

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VGA Links

• VGA Timing
• http//www.epanorama.net/documents/pc/vga_timing.h
  tml
• http//appsrv.cse.cuhk.edu.hk/ceg3480/Tutorial7/t
  ut7.doc
• Code (more complex than you want)
• http//www.stanford.edu/class/ee183/index.shtml
• Interesting
• http//www.howstuffworks.com/tv.htm
• http//computer.howstuffworks.com/monitor.htm
• http//www.howstuffworks.com/lcd.htm
• http//plc.cwru.edu/
• Liquid Crystals by S. Chandrasekhar, Cambridge
  Univ. Press